Simulation Results: edn/edn0

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 84.03 %
  • code
  • 80.30 %
  • assert
  • 95.01 %
  • func
  • 76.79 %
  • line
  • 97.17 %
  • branch
  • 89.96 %
  • cond
  • 83.69 %
  • toggle
  • 81.74 %
  • FSM
  • 48.92 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.270s 57.931us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.030s 47.963us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.060s 42.638us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 6.940s 542.097us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.320s 14.713us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.860s 24.375us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.060s 42.638us 1 1 100.00
edn_csr_aliasing 1.320s 14.713us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.550s 98.930us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.550s 98.930us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.550s 98.930us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.440s 21.281us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.390s 26.926us 1 1 100.00
errs 1 1 100.00
edn_err 1.290s 65.331us 1 1 100.00
disable 2 2 100.00
edn_disable 1.100s 12.401us 1 1 100.00
edn_disable_auto_req_mode 1.640s 113.791us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.470s 81.639us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.260s 12.851us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.270s 16.738us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.700s 95.738us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.700s 95.738us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.030s 47.963us 1 1 100.00
edn_csr_rw 1.060s 42.638us 1 1 100.00
edn_csr_aliasing 1.320s 14.713us 1 1 100.00
edn_same_csr_outstanding 1.190s 23.459us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.030s 47.963us 1 1 100.00
edn_csr_rw 1.060s 42.638us 1 1 100.00
edn_csr_aliasing 1.320s 14.713us 1 1 100.00
edn_same_csr_outstanding 1.190s 23.459us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.710s 588.207us 1 1 100.00
edn_tl_intg_err 2.200s 288.908us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.200s 80.867us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.390s 26.926us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.710s 588.207us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.710s 588.207us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.710s 588.207us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.710s 588.207us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.390s 26.926us 1 1 100.00
edn_sec_cm 5.710s 588.207us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.390s 26.926us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.200s 288.908us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 6.260s 199.186us 1 1 100.00