Simulation Results: edn/edn1

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 87.26 %
  • code
  • 83.78 %
  • assert
  • 98.18 %
  • func
  • 79.83 %
  • line
  • 98.03 %
  • branch
  • 92.86 %
  • cond
  • 88.00 %
  • toggle
  • 94.54 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.170s 34.934us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.150s 14.726us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.070s 13.787us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.830s 85.233us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.170s 13.258us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.170s 98.075us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.070s 13.787us 1 1 100.00
edn_csr_aliasing 1.170s 13.258us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.440s 124.525us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.440s 124.525us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.440s 124.525us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.300s 21.492us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.450s 79.159us 1 1 100.00
errs 1 1 100.00
edn_err 1.320s 19.262us 1 1 100.00
disable 2 2 100.00
edn_disable 1.200s 13.906us 1 1 100.00
edn_disable_auto_req_mode 1.630s 38.127us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.500s 1010.910us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.060s 71.613us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.170s 18.826us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.760s 219.450us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.760s 219.450us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.150s 14.726us 1 1 100.00
edn_csr_rw 1.070s 13.787us 1 1 100.00
edn_csr_aliasing 1.170s 13.258us 1 1 100.00
edn_same_csr_outstanding 1.710s 38.694us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.150s 14.726us 1 1 100.00
edn_csr_rw 1.070s 13.787us 1 1 100.00
edn_csr_aliasing 1.170s 13.258us 1 1 100.00
edn_same_csr_outstanding 1.710s 38.694us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.210s 718.848us 1 1 100.00
edn_tl_intg_err 3.060s 130.634us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.200s 17.016us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.450s 79.159us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.210s 718.848us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.210s 718.848us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.210s 718.848us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.210s 718.848us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.450s 79.159us 1 1 100.00
edn_sec_cm 3.210s 718.848us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.450s 79.159us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.060s 130.634us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 31.070s 3350.908us 1 1 100.00