Simulation Results: entropy_src/rng_4bits

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 75.08 %
  • code
  • 88.28 %
  • assert
  • 84.24 %
  • func
  • 52.72 %
  • block
  • 94.49 %
  • line
  • 97.16 %
  • branch
  • 86.75 %
  • toggle
  • 76.51 %
  • FSM
  • 92.71 %
Validation stages
V1
100.00%
V2
93.75%
V2S
85.71%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 34.955us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 3.000s 43.177us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 391.781us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 10.000s 951.585us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 1.000s 19.471us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 52.677us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 391.781us 1 1 100.00
entropy_src_csr_aliasing 1.000s 19.471us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 2 3 66.67
entropy_src_smoke 2.000s 34.955us 1 1 100.00
entropy_src_rng 243.000s 14083.189us 1 1 100.00
entropy_src_fw_ov 3600.000s 0.000us 0 1 0.00
firmware_mode 0 1 0.00
entropy_src_fw_ov 3600.000s 0.000us 0 1 0.00
rng_mode 1 1 100.00
entropy_src_rng 243.000s 14083.189us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 387.000s 13019.699us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 243.000s 14083.189us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 243.000s 14083.189us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 243.000s 14083.189us 1 1 100.00
entropy_src_intr 3.000s 341.059us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 243.000s 14083.189us 1 1 100.00
entropy_src_functional_alerts 6.000s 754.333us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 29.000s 18819.749us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 41.531us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 3.000s 67.899us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 46.207us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 22.275us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 113.891us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 113.891us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 3.000s 43.177us 1 1 100.00
entropy_src_csr_rw 2.000s 391.781us 1 1 100.00
entropy_src_csr_aliasing 1.000s 19.471us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 262.820us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 3.000s 43.177us 1 1 100.00
entropy_src_csr_rw 2.000s 391.781us 1 1 100.00
entropy_src_csr_aliasing 1.000s 19.471us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 262.820us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 109.459us 1 1 100.00
entropy_src_tl_intg_err 4.000s 107.676us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 243.000s 14083.189us 1 1 100.00
entropy_src_cfg_regwen 2.000s 15.227us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 243.000s 14083.189us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 243.000s 14083.189us 1 1 100.00
sec_cm_intersig_mubi 1 2 50.00
entropy_src_rng 243.000s 14083.189us 1 1 100.00
entropy_src_fw_ov 3600.000s 0.000us 0 1 0.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 41.531us 1 1 100.00
entropy_src_sec_cm 3.000s 109.459us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 41.531us 1 1 100.00
entropy_src_sec_cm 3.000s 109.459us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 243.000s 14083.189us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 41.531us 1 1 100.00
entropy_src_sec_cm 3.000s 109.459us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 41.531us 1 1 100.00
entropy_src_sec_cm 3.000s 109.459us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 41.531us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 6.000s 754.333us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 107.676us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 93.000s 13071.369us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 11.000s 511.205us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.alert_test 1 test run
entropy_src_stress_all_with_rand_reset 19542016413299641829946719216985764916054899869024812408364613357265787029062 121
UVM_INFO @ 511205207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
entropy_src_fw_ov 90781331478732683393972810349633063682962959864664477030611726582595820650322 None