Simulation Results: hmac

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 75.66 %
  • code
  • 86.43 %
  • assert
  • 97.38 %
  • func
  • 43.16 %
  • line
  • 99.54 %
  • branch
  • 99.02 %
  • cond
  • 96.25 %
  • toggle
  • 46.17 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 9.330s 3097.759us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.120s 44.897us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.900s 19.695us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.570s 1191.746us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 1.130s 18.757us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.730s 30.189us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.900s 19.695us 1 1 100.00
hmac_csr_aliasing 1.130s 18.757us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 82.290s 4581.709us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 63.200s 1772.850us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 12.070s 1748.339us 1 1 100.00
hmac_test_sha384_vectors 25.760s 865.554us 1 1 100.00
hmac_test_sha512_vectors 472.770s 21455.873us 1 1 100.00
hmac_test_hmac256_vectors 12.100s 339.958us 1 1 100.00
hmac_test_hmac384_vectors 15.930s 476.675us 1 1 100.00
hmac_test_hmac512_vectors 16.170s 1664.432us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 32.420s 3287.175us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 357.270s 4824.076us 1 1 100.00
error 1 1 100.00
hmac_error 6.030s 1255.906us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 43.420s 13784.917us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 9.330s 3097.759us 1 1 100.00
hmac_long_msg 82.290s 4581.709us 1 1 100.00
hmac_back_pressure 63.200s 1772.850us 1 1 100.00
hmac_datapath_stress 357.270s 4824.076us 1 1 100.00
hmac_burst_wr 32.420s 3287.175us 1 1 100.00
hmac_stress_all 145.460s 31644.475us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 9.330s 3097.759us 1 1 100.00
hmac_long_msg 82.290s 4581.709us 1 1 100.00
hmac_back_pressure 63.200s 1772.850us 1 1 100.00
hmac_datapath_stress 357.270s 4824.076us 1 1 100.00
hmac_wipe_secret 43.420s 13784.917us 1 1 100.00
hmac_test_sha256_vectors 12.070s 1748.339us 1 1 100.00
hmac_test_sha384_vectors 25.760s 865.554us 1 1 100.00
hmac_test_sha512_vectors 472.770s 21455.873us 1 1 100.00
hmac_test_hmac256_vectors 12.100s 339.958us 1 1 100.00
hmac_test_hmac384_vectors 15.930s 476.675us 1 1 100.00
hmac_test_hmac512_vectors 16.170s 1664.432us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 9.330s 3097.759us 1 1 100.00
hmac_long_msg 82.290s 4581.709us 1 1 100.00
hmac_back_pressure 63.200s 1772.850us 1 1 100.00
hmac_datapath_stress 357.270s 4824.076us 1 1 100.00
hmac_burst_wr 32.420s 3287.175us 1 1 100.00
hmac_error 6.030s 1255.906us 1 1 100.00
hmac_wipe_secret 43.420s 13784.917us 1 1 100.00
hmac_test_sha256_vectors 12.070s 1748.339us 1 1 100.00
hmac_test_sha384_vectors 25.760s 865.554us 1 1 100.00
hmac_test_sha512_vectors 472.770s 21455.873us 1 1 100.00
hmac_test_hmac256_vectors 12.100s 339.958us 1 1 100.00
hmac_test_hmac384_vectors 15.930s 476.675us 1 1 100.00
hmac_test_hmac512_vectors 16.170s 1664.432us 1 1 100.00
hmac_stress_all 145.460s 31644.475us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 145.460s 31644.475us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.910s 52.972us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.860s 15.754us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.410s 992.651us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.410s 992.651us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.120s 44.897us 1 1 100.00
hmac_csr_rw 0.900s 19.695us 1 1 100.00
hmac_csr_aliasing 1.130s 18.757us 1 1 100.00
hmac_same_csr_outstanding 2.860s 2427.545us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.120s 44.897us 1 1 100.00
hmac_csr_rw 0.900s 19.695us 1 1 100.00
hmac_csr_aliasing 1.130s 18.757us 1 1 100.00
hmac_same_csr_outstanding 2.860s 2427.545us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.380s 416.918us 1 1 100.00
hmac_tl_intg_err 2.220s 95.451us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.220s 95.451us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 9.330s 3097.759us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.480s 123.468us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 185.480s 16697.386us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.260s 27.550us 1 1 100.00