Simulation Results

Simulation Results: i2c

01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
84.73 %

code
78.19 %

assert
97.46 %

func
78.54 %

line
96.41 %

branch
92.33 %

cond
84.63 %

toggle
73.52 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		92.68%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	16.960s	1471.727us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	16.650s	845.096us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.030s	259.388us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.050s	24.989us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	5.020s	3758.419us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.140s	270.113us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.070s	404.659us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.050s	24.989us	1	1	100.00
	i2c_csr_aliasing	1.140s	270.113us	1	1	100.00

38/41 passed

92.68 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.130s	145.188us	0	1	0.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	743.730s	53789.121us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	506.430s	48082.159us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.920s	92.001us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	55.490s	12723.698us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	62.440s	3336.764us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.290s	456.425us	1	1	100.00
	i2c_host_fifo_fmt_empty	12.600s	3598.310us	1	1	100.00
	i2c_host_fifo_reset_rx	6.010s	156.034us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	122.590s	3967.201us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	6.080s	908.881us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.730s	36.480us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	3.180s	451.861us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	78.960s	52775.793us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	5.770s	1478.818us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	45.620s	1315.090us	1	1	100.00
	i2c_target_intr_smoke	7.560s	3299.396us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.760s	472.574us	1	1	100.00
	i2c_target_fifo_reset_tx	1.190s	198.261us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	20.670s	32913.302us	1	1	100.00
	i2c_target_stress_rd	45.620s	1315.090us	1	1	100.00
	i2c_target_intr_stress_wr	172.950s	19428.351us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	8.100s	20867.067us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	47.460s	1505.018us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.440s	2315.374us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	2.910s	355.201us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.000s	1521.550us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.860s	324.996us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	506.430s	48082.159us	1	1	100.00
	i2c_host_perf_precise	18.290s	2212.631us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	6.080s	908.881us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.160s	151.651us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.230s	918.568us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.120s	546.693us	1	1	100.00
	i2c_target_nack_txstretch	1.840s	805.766us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	4.740s	5074.588us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	2.480s	4644.313us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.920s	49.853us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.990s	18.248us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.630s	61.579us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.630s	61.579us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.030s	259.388us	1	1	100.00
	i2c_csr_rw	1.050s	24.989us	1	1	100.00
	i2c_csr_aliasing	1.140s	270.113us	1	1	100.00
	i2c_same_csr_outstanding	1.150s	36.345us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.030s	259.388us	1	1	100.00
	i2c_csr_rw	1.050s	24.989us	1	1	100.00
	i2c_csr_aliasing	1.140s	270.113us	1	1	100.00
	i2c_same_csr_outstanding	1.150s	36.345us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.460s	2230.541us	1	1	100.00
	i2c_sec_cm	1.170s	46.778us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.460s	2230.541us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	2.840s	110.388us	1
target_error_intr				1
	i2c_target_unexp_stop	1.110s	207.928us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	0.710s	251.466us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	57357329483470465959434154086233905169985244639003520787343662856914574128078	86	UVM_INFO @ 145188175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	61352369000707361625867667837284656632545429149076512797850501998881383300487	91	UVM_INFO @ 251465529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	2190441449134732084147222034984540343326691067543167434171702703569821967234	90	UVM_INFO @ 451860524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	34964369970179769987960037393638058566731810295096659634035408340279969093956	84	UVM_INFO @ 207928356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	97687425532439883624244851207011269511433241648580072079675517594821836743428	90	UVM_INFO @ 110387833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=, Comparison=CompareOpEq, exp_data=, call_count=3)				1 test run
	i2c_host_mode_toggle	4790299084781924283462050839142471792424395953434681086279698056486935996386	85	UVM_INFO @ 36480015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---