Simulation Results: keymgr_dpe/earlgrey

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 64.68 %
  • code
  • 82.24 %
  • assert
  • 97.21 %
  • func
  • 14.60 %
  • line
  • 97.35 %
  • branch
  • 93.77 %
  • cond
  • 86.00 %
  • toggle
  • 58.42 %
  • FSM
  • 75.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_dpe_smoke 9.280s 2770.071us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 1.470s 401.200us 1 1 100.00
csr_rw 1 1 100.00
keymgr_dpe_csr_rw 1.010s 50.850us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 10.800s 954.967us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 1.320s 14.097us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 1.410s 70.652us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_dpe_csr_rw 1.010s 50.850us 1 1 100.00
keymgr_dpe_csr_aliasing 1.320s 14.097us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
keymgr_dpe_intr_test 1.030s 11.168us 1 1 100.00
alert_test 1 1 100.00
keymgr_dpe_alert_test 1.160s 45.667us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_dpe_tl_errors 1.940s 106.103us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_dpe_tl_errors 1.940s 106.103us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_dpe_csr_hw_reset 1.470s 401.200us 1 1 100.00
keymgr_dpe_csr_rw 1.010s 50.850us 1 1 100.00
keymgr_dpe_csr_aliasing 1.320s 14.097us 1 1 100.00
keymgr_dpe_same_csr_outstanding 2.150s 327.949us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_dpe_csr_hw_reset 1.470s 401.200us 1 1 100.00
keymgr_dpe_csr_rw 1.010s 50.850us 1 1 100.00
keymgr_dpe_csr_aliasing 1.320s 14.097us 1 1 100.00
keymgr_dpe_same_csr_outstanding 2.150s 327.949us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
keymgr_dpe_sec_cm 12.080s 1212.286us 1 1 100.00
keymgr_dpe_tl_intg_err 2.950s 212.316us 1 1 100.00
shadow_reg_update_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 2.480s 103.021us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
keymgr_dpe_shadow_reg_errors 2.480s 103.021us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 2.480s 103.021us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
keymgr_dpe_shadow_reg_errors 2.480s 103.021us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 1.030s 7.846us 0 1 0.00
prim_count_check 1 1 100.00
keymgr_dpe_sec_cm 12.080s 1212.286us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_dpe_sec_cm 12.080s 1212.286us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(reg2hw.control_shadowed.slot_dst_sel.q < NumInstHwSlot)' 1 test run
keymgr_dpe_shadow_reg_errors 1162754960460184598042864879122001863464521391675505373874751828950835323816 84
UVM_ERROR @ 103020991 ps: (keymgr_dpe.sv:321) [ASSERT FAILED] DstSelInRange_A
UVM_INFO @ 103020991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(reg2hw.control_shadowed.slot_src_sel.q < NumInstHwSlot)' 1 test run
keymgr_dpe_shadow_reg_errors_with_csr_rw 111224369639871519185074595543737577291531059259673236378897747290939329590854 83
UVM_ERROR @ 7846038 ps: (keymgr_dpe.sv:320) [ASSERT FAILED] SrcSelInRange_A
UVM_INFO @ 7846038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---