Simulation Results: lc_ctrl/volatile_unlock_enabled

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.42 %
  • code
  • 83.93 %
  • assert
  • 94.69 %
  • func
  • 92.65 %
  • line
  • 97.17 %
  • branch
  • 93.57 %
  • cond
  • 79.42 %
  • toggle
  • 85.92 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.710s 120.358us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.160s 35.837us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.140s 101.528us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.900s 196.816us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 20.999us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.680s 192.993us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.140s 101.528us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 20.999us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.190s 132.618us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.150s 228.716us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.030s 75.740us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.920s 117.400us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.050s 524.586us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 10.230s 484.130us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.050s 524.586us 1 1 100.00
lc_ctrl_prog_failure 1.920s 117.400us 1 1 100.00
lc_ctrl_errors 10.230s 484.130us 1 1 100.00
lc_ctrl_security_escalation 5.940s 706.336us 1 1 100.00
lc_ctrl_jtag_state_failure 24.220s 7892.988us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.410s 487.300us 1 1 100.00
lc_ctrl_jtag_errors 28.660s 6064.376us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.370s 381.728us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.700s 1422.924us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.410s 487.300us 1 1 100.00
lc_ctrl_jtag_errors 28.660s 6064.376us 1 1 100.00
lc_ctrl_jtag_access 7.190s 911.878us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.670s 4915.506us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.170s 378.856us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.730s 55.561us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.930s 871.251us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 1.700s 50.948us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.540s 103.598us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.370s 115.770us 1 1 100.00
lc_ctrl_jtag_alert_test 1.300s 184.572us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.800s 541.131us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.420s 32.767us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 41.960s 9437.317us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.130s 16.280us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.070s 90.353us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.070s 90.353us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.160s 35.837us 1 1 100.00
lc_ctrl_csr_rw 1.140s 101.528us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 20.999us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.210s 94.418us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.160s 35.837us 1 1 100.00
lc_ctrl_csr_rw 1.140s 101.528us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 20.999us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.210s 94.418us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 8.050s 322.509us 1 1 100.00
lc_ctrl_tl_intg_err 1.690s 121.373us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.690s 121.373us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.150s 228.716us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.050s 524.586us 1 1 100.00
lc_ctrl_sec_cm 8.050s 322.509us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.050s 524.586us 1 1 100.00
lc_ctrl_sec_cm 8.050s 322.509us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.050s 524.586us 1 1 100.00
lc_ctrl_sec_cm 8.050s 322.509us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.050s 524.586us 1 1 100.00
lc_ctrl_sec_cm 8.050s 322.509us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.050s 524.586us 1 1 100.00
lc_ctrl_sec_cm 8.050s 322.509us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.050s 524.586us 1 1 100.00
lc_ctrl_sec_cm 8.050s 322.509us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.050s 524.586us 1 1 100.00
lc_ctrl_sec_cm 8.050s 322.509us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.050s 524.586us 1 1 100.00
lc_ctrl_sec_cm 8.050s 322.509us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.940s 706.336us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.190s 132.618us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.700s 1422.924us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.290s 597.271us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.290s 597.271us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.200s 338.240us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.190s 201.581us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.190s 201.581us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 15.240s 3140.641us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 57569294047074564193928053800055996467728088724063570130850221298342536819984 2874
UVM_INFO @ 3140641431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---