Simulation Results: otbn

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 89.64 %
  • code
  • 81.81 %
  • assert
  • 89.66 %
  • func
  • 97.46 %
  • block
  • 97.71 %
  • line
  • 97.94 %
  • branch
  • 81.66 %
  • toggle
  • 81.43 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 15.000s 50.395us 1 1 100.00
otbn_smoke_vectorized 10.000s 45.265us 1 1 100.00
single_binary 1 1 100.00
otbn_single 10.000s 25.267us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 14.711us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 51.246us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 9.000s 173.658us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 21.273us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 10.000s 271.073us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 51.246us 1 1 100.00
otbn_csr_aliasing 4.000s 21.273us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 77.000s 3680.191us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 38.000s 560.678us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 35.000s 77.996us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 81.000s 987.466us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 60.000s 727.060us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 105.000s 308.533us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 11.000s 22.303us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 9.000s 17.384us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 12.000s 19.107us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 7.000s 16.013us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 14.218us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 8.000s 474.116us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 8.000s 474.116us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 5.000s 14.711us 1 1 100.00
otbn_csr_rw 5.000s 51.246us 1 1 100.00
otbn_csr_aliasing 4.000s 21.273us 1 1 100.00
otbn_same_csr_outstanding 5.000s 25.270us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 5.000s 14.711us 1 1 100.00
otbn_csr_rw 5.000s 51.246us 1 1 100.00
otbn_csr_aliasing 4.000s 21.273us 1 1 100.00
otbn_same_csr_outstanding 5.000s 25.270us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 13.000s 25.607us 1 1 100.00
otbn_dmem_err 9.000s 42.448us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 12.000s 56.789us 1 1 100.00
otbn_controller_ispr_rdata_err 13.000s 18.944us 1 1 100.00
otbn_mac_bignum_acc_err 12.000s 197.952us 1 1 100.00
otbn_urnd_err 8.000s 17.970us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 8.000s 10.381us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 13.000s 34.164us 1 1 100.00
otbn_non_sec_partial_wipe 0 1 0.00
otbn_partial_wipe 6.000s 13.711us 0 1 0.00
tl_intg_err 2 2 100.00
otbn_sec_cm 179.000s 2791.312us 1 1 100.00
otbn_tl_intg_err 17.000s 225.375us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 54.000s 136.260us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 179.000s 2791.312us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 179.000s 2791.312us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 15.000s 50.395us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 9.000s 42.448us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 13.000s 25.607us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 17.000s 225.375us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 11.000s 22.303us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 13.000s 25.607us 1 1 100.00
otbn_dmem_err 9.000s 42.448us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 17.384us 1 1 100.00
otbn_illegal_mem_acc 8.000s 10.381us 1 1 100.00
otbn_sec_cm 179.000s 2791.312us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 179.000s 2791.312us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 10.000s 25.267us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 13.000s 25.607us 1 1 100.00
otbn_dmem_err 9.000s 42.448us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 17.384us 1 1 100.00
otbn_illegal_mem_acc 8.000s 10.381us 1 1 100.00
otbn_sec_cm 179.000s 2791.312us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 179.000s 2791.312us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 11.000s 22.303us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 13.000s 25.607us 1 1 100.00
otbn_dmem_err 9.000s 42.448us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 17.384us 1 1 100.00
otbn_illegal_mem_acc 8.000s 10.381us 1 1 100.00
otbn_sec_cm 179.000s 2791.312us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 179.000s 2791.312us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 10.000s 25.267us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 15.000s 35.502us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 9.000s 22.487us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 33.000s 673.203us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 33.000s 673.203us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 12.000s 39.345us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 179.000s 2791.312us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 179.000s 2791.312us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 11.000s 386.372us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 179.000s 2791.312us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 179.000s 2791.312us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 41.716us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 41.716us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 26.000s 39.197us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 10.000s 25.267us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 10.000s 25.267us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 10.000s 25.267us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 60.000s 727.060us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 10.000s 25.267us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 10.000s 25.267us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 15.000s 49.641us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 10.000s 25.267us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 179.000s 2791.312us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 16.000s 52.621us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_base_vseq.sv:349) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 111763939060295801318735426156159260839227815379180583691862986117261414247136 171
UVM_INFO @ 52621012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:322) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_partial_wipe 55022596528829867820688466360337520476531371868461150123126644963612568078221 114
UVM_INFO @ 13710741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 66211157553701002360052225196287651641915374282770578060087903311553422238578 156
UVM_INFO @ 136260410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---