Simulation Results: otp_ctrl

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 81.93 %
  • code
  • 79.03 %
  • assert
  • 94.38 %
  • func
  • 72.38 %
  • line
  • 88.52 %
  • branch
  • 83.41 %
  • cond
  • 90.33 %
  • toggle
  • 87.25 %
  • FSM
  • 45.66 %
Validation stages
V1
100.00%
V2
90.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.240s 66.107us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 6.740s 301.611us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.610s 127.589us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.790s 49.908us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 22.290s 8761.426us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.410s 101.100us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.760s 75.843us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.790s 49.908us 1 1 100.00
otp_ctrl_csr_aliasing 2.410s 101.100us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.500s 71.309us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.980s 71.170us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 17.890s 1657.706us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.400s 251.493us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 43.240s 9568.173us 1 1 100.00
otp_ctrl_check_fail 4.240s 181.289us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.040s 305.336us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 21.320s 1671.820us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 13.410s 730.553us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 15.700s 1702.284us 1 1 100.00
otp_ctrl_parallel_lc_esc 7.950s 935.865us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 27.170s 6783.084us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 2.680s 71.051us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 15.590s 1982.541us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 222.040s 21482.509us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.350s 39.098us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.200s 90.295us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.590s 253.467us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.590s 253.467us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.610s 127.589us 1 1 100.00
otp_ctrl_csr_rw 1.790s 49.908us 1 1 100.00
otp_ctrl_csr_aliasing 2.410s 101.100us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.010s 71.520us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.610s 127.589us 1 1 100.00
otp_ctrl_csr_rw 1.790s 49.908us 1 1 100.00
otp_ctrl_csr_aliasing 2.410s 101.100us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.010s 71.520us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
otp_ctrl_tl_intg_err 19.630s 1337.040us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 19.630s 1337.040us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 6.740s 301.611us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 6.740s 301.611us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.950s 935.865us 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.950s 935.865us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.950s 935.865us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.950s 935.865us 1 1 100.00
otp_ctrl_macro_errs 2.680s 71.051us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.950s 935.865us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.950s 935.865us 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.950s 935.865us 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.950s 935.865us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.950s 935.865us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.950s 935.865us 1 1 100.00
otp_ctrl_macro_errs 2.680s 71.051us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.950s 935.865us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.950s 935.865us 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.400s 251.493us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 4.240s 181.289us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 21.320s 1671.820us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 21.320s 1671.820us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 21.320s 1671.820us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 21.320s 1671.820us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 21.320s 1671.820us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 6.740s 301.611us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 21.320s 1671.820us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 6.740s 301.611us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.090s 21093.828us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.040s 305.336us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 6.740s 301.611us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 6.740s 301.611us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 2.680s 71.051us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 13.110s 8074.272us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 16.200s 7342.888us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 55109012900167428022304416796415385703833578100394354595895877267660824003873 1375
UVM_INFO @ 71051062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1306) scoreboard [scoreboard] pwr_otp_idle output is * while expect * within * cycles 1 test run
otp_ctrl_parallel_key_req 62647726745962529172910217942258163708342804938027003762614470951793206274124 7549
UVM_INFO @ 730552809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all_with_rand_reset 78825847003048699765154391077091441710649822961072139991282924823730492977867 3231
UVM_INFO @ 7342887853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---