Simulation Results: pwrmgr

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 96.07 %
  • code
  • 94.43 %
  • assert
  • 97.39 %
  • func
  • 96.38 %
  • line
  • 98.93 %
  • branch
  • 95.62 %
  • cond
  • 93.78 %
  • toggle
  • 89.83 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
72.73%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.730s 61.918us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.920s 37.035us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.700s 41.539us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.820s 684.338us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.980s 118.488us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.940s 74.368us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.700s 41.539us 1 1 100.00
pwrmgr_csr_aliasing 0.980s 118.488us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.960s 259.743us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.960s 259.743us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.900s 31.621us 1 1 100.00
pwrmgr_lowpower_invalid 0.710s 46.451us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.760s 25.625us 1 1 100.00
pwrmgr_reset_invalid 0.980s 125.491us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.760s 25.625us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.040s 147.485us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.870s 220.399us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 1.110s 124.157us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 4.640s 885.707us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.590s 48.291us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.930s 142.680us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.930s 142.680us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.920s 37.035us 1 1 100.00
pwrmgr_csr_rw 0.700s 41.539us 1 1 100.00
pwrmgr_csr_aliasing 0.980s 118.488us 1 1 100.00
pwrmgr_same_csr_outstanding 1.010s 57.332us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.920s 37.035us 1 1 100.00
pwrmgr_csr_rw 0.700s 41.539us 1 1 100.00
pwrmgr_csr_aliasing 0.980s 118.488us 1 1 100.00
pwrmgr_same_csr_outstanding 1.010s 57.332us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 3600.027s 0.000us 0 1 0.00
pwrmgr_sec_cm 3600.028s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 3600.028s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 3600.028s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 3600.027s 0.000us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.650s 830.624us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 1.040s 147.485us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.740s 1350.072us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.930s 162.696us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.750s 30.017us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 3600.028s 0.000us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 3600.028s 0.000us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 3600.028s 0.000us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.700s 27.674us 1 1 100.00
sec_cm_main_pd_rst_local_esc 0 1 0.00
pwrmgr_glitch 3600.039s 0.000us 0 1 0.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.280s 287.232us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.700s 41.539us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.700s 41.539us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.990s 377.041us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 3600.024s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 4 test runs
pwrmgr_glitch 80068437769450792273494657712225384828705075256691242902512202163306882937983 None
pwrmgr_tl_intg_err 114187519360524460414181167371320277733737945846905480183635254811079380056660 None
pwrmgr_sec_cm 6380170584018719377511899190831648141617928249031045601474216872758518103830 None
pwrmgr_stress_all_with_rand_reset 88938537338844626071905706349565407749118199956067294635296114028868683696756 None