Simulation Results: rom_ctrl/192kb

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 92.29 %
  • code
  • 87.88 %
  • assert
  • 97.39 %
  • func
  • 91.61 %
  • line
  • 97.63 %
  • branch
  • 97.83 %
  • cond
  • 95.70 %
  • toggle
  • 94.93 %
  • FSM
  • 53.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 20.140s 1071.263us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 26.310s 72.691us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 11.350s 64.153us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 11.740s 119.019us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 11.810s 58.513us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 11.870s 61.907us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 11.350s 64.153us 1 1 100.00
rom_ctrl_csr_aliasing 11.810s 58.513us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 10.920s 57.784us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 10.670s 69.334us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 11.810s 4.938us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 91.370s 6135.173us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 19.340s 62.832us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 10.530s 96.534us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 18.380s 1068.111us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 18.380s 1068.111us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 26.310s 72.691us 1 1 100.00
rom_ctrl_csr_rw 11.350s 64.153us 1 1 100.00
rom_ctrl_csr_aliasing 11.810s 58.513us 1 1 100.00
rom_ctrl_same_csr_outstanding 20.290s 148.393us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 26.310s 72.691us 1 1 100.00
rom_ctrl_csr_rw 11.350s 64.153us 1 1 100.00
rom_ctrl_csr_aliasing 11.810s 58.513us 1 1 100.00
rom_ctrl_same_csr_outstanding 20.290s 148.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 223.200s 200000.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 57.880s 84.640us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 1691.570s 880.284us 1 1 100.00
rom_ctrl_tl_intg_err 193.980s 205.752us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 1691.570s 880.284us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 1691.570s 880.284us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 223.200s 200000.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 223.200s 200000.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 223.200s 200000.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 223.200s 200000.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 223.200s 200000.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 1691.570s 880.284us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 1691.570s 880.284us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 20.140s 1071.263us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 20.140s 1071.263us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 20.140s 1071.263us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 193.980s 205.752us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 223.200s 200000.000us 0 1 0.00
rom_ctrl_kmac_err_chk 19.340s 62.832us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 223.200s 200000.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 223.200s 200000.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 223.200s 200000.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 57.880s 84.640us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 1691.570s 880.284us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 58.150s 6124.288us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 93560914358376581179360542604916536316965218721314458958056311052988448975813 85
UVM_INFO @ 4938052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rom_ctrl_corrupt_sig_fatal_chk 48595986561722670718260231982020448396933762255126494087671379120237572660522 92
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---