Simulation Results: rstmgr

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 96.58 %
  • code
  • 99.17 %
  • assert
  • 98.53 %
  • func
  • 92.04 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.33 %
  • toggle
  • 99.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.210s 138.359us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.040s 127.619us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.060s 65.457us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.020s 385.994us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 0.970s 63.905us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.740s 214.542us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.060s 65.457us 1 1 100.00
rstmgr_csr_aliasing 0.970s 63.905us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.110s 175.070us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.120s 503.752us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.810s 91.530us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 6.870s 2120.348us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 6.870s 2120.348us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 6.870s 2120.348us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 6.870s 2120.348us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 20.970s 6537.381us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.980s 83.166us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.120s 277.497us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.120s 277.497us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.040s 127.619us 1 1 100.00
rstmgr_csr_rw 1.060s 65.457us 1 1 100.00
rstmgr_csr_aliasing 0.970s 63.905us 1 1 100.00
rstmgr_same_csr_outstanding 1.080s 98.450us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.040s 127.619us 1 1 100.00
rstmgr_csr_rw 1.060s 65.457us 1 1 100.00
rstmgr_csr_aliasing 0.970s 63.905us 1 1 100.00
rstmgr_same_csr_outstanding 1.080s 98.450us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 11.550s 8455.173us 1 1 100.00
rstmgr_tl_intg_err 1.640s 495.318us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 11.550s 8455.173us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 11.550s 8455.173us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.640s 495.318us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.220s 195.082us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 7.350s 2804.880us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.050s 301.199us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 11.550s 8455.173us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.060s 65.457us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.060s 65.457us 1 1 100.00