Simulation Results: rv_timer

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 95.93 %
  • code
  • 94.66 %
  • assert
  • 98.41 %
  • func
  • 94.71 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.660s 114.192us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.650s 13.529us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.560s 29.270us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.120s 706.359us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.680s 14.910us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.830s 104.633us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.560s 29.270us 1 1 100.00
rv_timer_csr_aliasing 0.680s 14.910us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 0.610s 42.281us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 1.110s 2924.925us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 17.670s 35703.236us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 17.670s 35703.236us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 4.960s 2547.182us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.630s 16.330us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.610s 54.263us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.430s 655.387us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.430s 655.387us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.650s 13.529us 1 1 100.00
rv_timer_csr_rw 0.560s 29.270us 1 1 100.00
rv_timer_csr_aliasing 0.680s 14.910us 1 1 100.00
rv_timer_same_csr_outstanding 0.710s 100.444us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.650s 13.529us 1 1 100.00
rv_timer_csr_rw 0.560s 29.270us 1 1 100.00
rv_timer_csr_aliasing 0.680s 14.910us 1 1 100.00
rv_timer_same_csr_outstanding 0.710s 100.444us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.810s 68.494us 1 1 100.00
rv_timer_tl_intg_err 1.240s 293.424us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.240s 293.424us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.600s 66.712us 0 1 0.00
max_value 1 1 100.00
rv_timer_max 0.640s 11.749us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 7.070s 4356.183us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 58838398400748476561095772880566443965739399774868877881572213041272950217456 81
UVM_INFO @ 66712339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---