Simulation Results: spi_device/1r1w

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 85.57 %
  • code
  • 91.31 %
  • assert
  • 95.40 %
  • func
  • 69.99 %
  • line
  • 98.84 %
  • branch
  • 98.11 %
  • cond
  • 95.96 %
  • toggle
  • 74.30 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 77.170s 19042.928us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.970s 115.980us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.070s 100.063us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 28.130s 3037.784us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 1.540s 51.412us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.000s 484.246us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.070s 100.063us 1 1 100.00
spi_device_csr_aliasing 1.540s 51.412us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.720s 71.958us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.140s 70.358us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.760s 45.883us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.870s 6.466us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.850s 7.747us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.410s 154.285us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.410s 154.285us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 5.540s 10364.190us 1 1 100.00
spi_device_tpm_sts_read 0.880s 231.651us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 32.760s 37969.807us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 6.990s 7475.368us 1 1 100.00
spi_device_flash_all 85.030s 18137.450us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.950s 5407.410us 1 1 100.00
spi_device_flash_all 85.030s 18137.450us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.950s 5407.410us 1 1 100.00
spi_device_flash_all 85.030s 18137.450us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 85.030s 18137.450us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.030s 173.876us 1 1 100.00
spi_device_flash_all 85.030s 18137.450us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.030s 173.876us 1 1 100.00
spi_device_flash_all 85.030s 18137.450us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.030s 173.876us 1 1 100.00
spi_device_flash_all 85.030s 18137.450us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.030s 173.876us 1 1 100.00
spi_device_flash_all 85.030s 18137.450us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.030s 173.876us 1 1 100.00
spi_device_flash_all 85.030s 18137.450us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 15.870s 17862.435us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 51.290s 7851.775us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 51.290s 7851.775us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 51.290s 7851.775us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 19.810s 9849.501us 1 1 100.00
spi_device_read_buffer_direct 5.250s 914.181us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 51.290s 7851.775us 1 1 100.00
spi_device_flash_all 85.030s 18137.450us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 85.030s 18137.450us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 85.030s 18137.450us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 7.430s 1373.994us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 7.430s 1373.994us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 57.640s 13990.950us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 77.170s 19042.928us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 60.050s 17362.173us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 82.450s 12559.643us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.840s 23.917us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.870s 34.590us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.290s 67.837us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.290s 67.837us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.970s 115.980us 1 1 100.00
spi_device_csr_rw 2.070s 100.063us 1 1 100.00
spi_device_csr_aliasing 1.540s 51.412us 1 1 100.00
spi_device_same_csr_outstanding 3.270s 200.622us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.970s 115.980us 1 1 100.00
spi_device_csr_rw 2.070s 100.063us 1 1 100.00
spi_device_csr_aliasing 1.540s 51.412us 1 1 100.00
spi_device_same_csr_outstanding 3.270s 200.622us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.340s 188.381us 1 1 100.00
spi_device_tl_intg_err 6.020s 365.800us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 6.020s 365.800us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1661) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 6998299708767855437386238114073565623107375000203839448085150332679592281976 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 3841033 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 3841033 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[931])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 98901025766782816711084640424485922543152734058286709913464932848194373352910 76
UVM_ERROR @ 5003836 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb1 [10110001] vs 0x0 [0])
UVM_ERROR @ 5063836 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc1 [11000001] vs 0x0 [0])
UVM_ERROR @ 5064836 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x34c [1101001100] vs 0x0 [0])
UVM_ERROR @ 5155836 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x14d [101001101] vs 0x0 [0])