Simulation Results: spi_host

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.74 %
  • code
  • 91.30 %
  • assert
  • 95.27 %
  • func
  • 88.66 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 18.000s 2606.411us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 40.914us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 45.795us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 634.608us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 10.000s 30.081us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 25.830us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 45.795us 1 1 100.00
spi_host_csr_aliasing 10.000s 30.081us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 87.020us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 21.523us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 10.000s 65.368us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 11.000s 78.042us 1 1 100.00
spi_host_error_cmd 10.000s 23.591us 1 1 100.00
spi_host_event 41.000s 26169.036us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 10.000s 55.500us 1 1 100.00
speed 1 1 100.00
spi_host_speed 10.000s 55.500us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 10.000s 55.500us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 567.000s 41074.055us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 39.000s 1122.788us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 10.000s 29.486us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 10.000s 55.500us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 10.000s 55.500us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 18.000s 2606.411us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 18.000s 2606.411us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 35.000s 4833.252us 1 1 100.00
spien 1 1 100.00
spi_host_spien 13.000s 2452.781us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 40.000s 9014.983us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 10.000s 158.366us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 11.000s 78.042us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 10.000s 37.457us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 32.126us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 121.775us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 121.775us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 40.914us 1 1 100.00
spi_host_csr_rw 1.000s 45.795us 1 1 100.00
spi_host_csr_aliasing 10.000s 30.081us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 36.170us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 40.914us 1 1 100.00
spi_host_csr_rw 1.000s 45.795us 1 1 100.00
spi_host_csr_aliasing 10.000s 30.081us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 36.170us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 227.418us 1 1 100.00
spi_host_sec_cm 10.000s 46.830us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 227.418us 1 1 100.00