Simulation Results: sram_ctrl/main

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.06 %
  • code
  • 95.09 %
  • assert
  • 97.28 %
  • func
  • 92.80 %
  • block
  • 94.48 %
  • line
  • 95.64 %
  • branch
  • 92.86 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 354.948us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 18.030us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.945us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 60.684us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 18.389us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 710.459us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 13.945us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 18.389us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 173.000s 44401.864us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 74.000s 3006.441us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 16.000s 7949.270us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 138.000s 3091.828us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 193.000s 15464.597us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 93.000s 206062.581us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 19.000s 6112.183us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 12.000s 5752.733us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 7.000s 1433.586us 1 1 100.00
sram_ctrl_partial_access_b2b 188.000s 39881.535us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 6.000s 673.175us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 2668.926us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 2486.832us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 13.000s 6146.317us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 354.732us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 4.000s 354.948us 1 1 100.00
sram_ctrl_partial_access 7.000s 1433.586us 1 1 100.00
sram_ctrl_access_during_key_req 93.000s 206062.581us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 215.000s 22771.409us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 15.953us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 25.536us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 25.536us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 18.030us 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.945us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 18.389us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 39.357us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 18.030us 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.945us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 18.389us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 39.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 36.000s 28185.980us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 674.612us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 340.101us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 674.612us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 340.101us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 13.000s 6146.317us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 13.000s 6146.317us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.945us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 12.000s 5752.733us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 5752.733us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 5752.733us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 19.000s 6112.183us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 36.000s 28185.980us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 354.948us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 354.948us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 12.000s 5752.733us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 674.612us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 19.000s 6112.183us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 674.612us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 674.612us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 354.948us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 674.612us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 13.000s 1407.986us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 115094272325690320136175450489393443094128824056400301332473556279286835444544 None
sram_ctrl_mubi_enc_err 24277394909432034895549984228916562995952258081508860632193361180152822075936 None