Simulation Results: sram_ctrl/ret

 
01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.99 %
  • code
  • 81.50 %
  • assert
  • 98.08 %
  • func
  • 93.40 %
  • block
  • 91.85 %
  • line
  • 93.41 %
  • branch
  • 87.60 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
87.50%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 47.442us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 14.194us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.001us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 100.032us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 11.175us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 23.204us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 15.001us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 11.175us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 13.000s 893.519us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 66.340us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 14.000s 395.718us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 200.000s 32744.806us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 10.000s 1935.153us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 34.000s 3158.973us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 12.000s 9382.724us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 15.000s 596.296us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 202.003us 1 1 100.00
sram_ctrl_partial_access_b2b 271.000s 19364.531us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 184.292us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 73.082us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 80.075us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 3.000s 330.640us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 33.051us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 2.000s 47.442us 1 1 100.00
sram_ctrl_partial_access 2.000s 202.003us 1 1 100.00
sram_ctrl_access_during_key_req 34.000s 3158.973us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 26.000s 849.048us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 15.683us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 101.012us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 101.012us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 14.194us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.001us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 11.175us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 53.971us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 14.194us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.001us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 11.175us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 53.971us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 2908.457us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 241.743us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 125.718us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 241.743us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 125.718us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 330.640us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 330.640us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.001us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 15.000s 596.296us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 15.000s 596.296us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 15.000s 596.296us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 12.000s 9382.724us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 2908.457us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 47.442us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 47.442us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 15.000s 596.296us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 241.743us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 12.000s 9382.724us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 241.743us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 241.743us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 47.442us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 241.743us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 36.000s 2817.696us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 13518196897612716841591900982958239873868975959782565237347898745418684209632 None
sram_ctrl_mubi_enc_err 113784018766390852201457018263700049456952429532043384117679445859002050740763 None
UVM_ERROR (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 107828199981863715730926533816084025994623911522559150215019635723209293229817 88
UVM_INFO @ 23203935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---