Simulation Results

Simulation Results: uart

01/09/2026 15:30:38 DVSim: v1.52.0 sha: fbc48f8 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
83.76 %

code
92.55 %

assert
98.56 %

func
60.16 %

line
99.48 %

branch
98.14 %

cond
97.90 %

toggle
74.67 %

Validation stages

V1		100.00%
V2		95.45%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	2.770s	547.694us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.620s	22.239us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	0.600s	13.686us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	1.260s	138.747us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	0.690s	25.739us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	0.820s	78.908us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	0.600s	13.686us	1	1	100.00
	uart_csr_aliasing	0.690s	25.739us	1	1	100.00

21/22 passed

95.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	6.210s	10585.185us	1	1	100.00
parity				2	2	100.00
	uart_smoke	2.770s	547.694us	1	1	100.00
	uart_tx_rx	6.210s	10585.185us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	4.520s	6460.857us	1	1	100.00
	uart_rx_parity_err	58.760s	165657.510us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	6.210s	10585.185us	1	1	100.00
	uart_intr	4.520s	6460.857us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	33.780s	37346.164us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	34.530s	130905.283us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	18.230s	156488.212us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	4.520s	6460.857us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	4.520s	6460.857us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	4.520s	6460.857us	1	1	100.00
perf				1	1	100.00
	uart_perf	372.370s	14632.492us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	1.230s	973.316us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	1.230s	973.316us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	6.900s	81144.993us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	1.310s	4173.497us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	17.790s	5951.438us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	7.400s	5749.903us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	558.160s	98103.458us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	238.400s	168256.976us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	0.770s	19.424us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	0.580s	39.516us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	1.090s	54.498us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	1.090s	54.498us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	0.620s	22.239us	1	1	100.00
	uart_csr_rw	0.600s	13.686us	1	1	100.00
	uart_csr_aliasing	0.690s	25.739us	1	1	100.00
	uart_same_csr_outstanding	0.900s	23.263us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	0.620s	22.239us	1	1	100.00
	uart_csr_rw	0.600s	13.686us	1	1	100.00
	uart_csr_aliasing	0.690s	25.739us	1	1	100.00
	uart_same_csr_outstanding	0.900s	23.263us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	0.950s	85.123us	1	1	100.00
	uart_tl_intg_err	1.390s	474.521us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	1.390s	474.521us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	50.830s	5134.143us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:390) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				1 test run
	uart_noise_filter	72009231852403249446553522919677039063393067749805211184600623320556322194341	83	UVM_ERROR @ 77967992986 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 77975392986 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 78472392986 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 78472392986 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0