Simulation Results: adc_ctrl

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 70.71 %
  • code
  • 96.79 %
  • assert
  • 96.60 %
  • func
  • 18.74 %
  • line
  • 99.05 %
  • branch
  • 98.51 %
  • cond
  • 94.50 %
  • toggle
  • 100.00 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 13.180s 5885.790us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 3.940s 1276.799us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.910s 454.394us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 18.830s 26495.666us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.140s 526.937us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.530s 586.874us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.910s 454.394us 1 1 100.00
adc_ctrl_csr_aliasing 2.140s 526.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 8.470s 34639.251us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 78.180s 57810.623us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 5.140s 19465.901us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 102.770s 52824.208us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 34.160s 72944.261us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 30.410s 74074.158us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 20.630s 20950.429us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 21.640s 44519.673us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 6.790s 4652.479us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 89.660s 45963.776us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 177.950s 89275.720us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 261.830s 142127.776us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 2.040s 482.181us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.420s 370.021us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.410s 472.282us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.410s 472.282us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 3.940s 1276.799us 1 1 100.00
adc_ctrl_csr_rw 1.910s 454.394us 1 1 100.00
adc_ctrl_csr_aliasing 2.140s 526.937us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.400s 4466.104us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 3.940s 1276.799us 1 1 100.00
adc_ctrl_csr_rw 1.910s 454.394us 1 1 100.00
adc_ctrl_csr_aliasing 2.140s 526.937us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.400s 4466.104us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 3.790s 4180.917us 1 1 100.00
adc_ctrl_tl_intg_err 10.270s 4229.057us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 10.270s 4229.057us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 6.820s 2338.487us 1 1 100.00