Simulation Results: aes/masked

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.87 %
  • code
  • 94.59 %
  • assert
  • 98.23 %
  • func
  • 73.80 %
  • block
  • 94.86 %
  • line
  • 95.82 %
  • branch
  • 88.99 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 70.427us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 191.512us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 65.048us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 81.013us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 482.604us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 102.175us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 137.386us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 81.013us 1 1 100.00
aes_csr_aliasing 3.000s 102.175us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 191.512us 1 1 100.00
aes_config_error 3.000s 117.685us 1 1 100.00
aes_stress 4.000s 364.020us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 191.512us 1 1 100.00
aes_config_error 3.000s 117.685us 1 1 100.00
aes_stress 4.000s 364.020us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 364.020us 1 1 100.00
aes_b2b 16.000s 873.973us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 364.020us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 191.512us 1 1 100.00
aes_config_error 3.000s 117.685us 1 1 100.00
aes_stress 4.000s 364.020us 1 1 100.00
aes_alert_reset 3.000s 141.275us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 70.160us 1 1 100.00
aes_config_error 3.000s 117.685us 1 1 100.00
aes_alert_reset 3.000s 141.275us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 90.207us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 9.000s 219.518us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 141.275us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 364.020us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 364.020us 1 1 100.00
aes_sideload 3.000s 63.447us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 90.126us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 21.000s 3981.079us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 78.193us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 402.144us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 402.144us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 65.048us 1 1 100.00
aes_csr_rw 2.000s 81.013us 1 1 100.00
aes_csr_aliasing 3.000s 102.175us 1 1 100.00
aes_same_csr_outstanding 1.000s 61.069us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 65.048us 1 1 100.00
aes_csr_rw 2.000s 81.013us 1 1 100.00
aes_csr_aliasing 3.000s 102.175us 1 1 100.00
aes_same_csr_outstanding 1.000s 61.069us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 3.000s 68.315us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 7.000s 419.660us 0 1 0.00
aes_control_fi 2.000s 98.600us 1 1 100.00
aes_cipher_fi 2.000s 64.333us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 84.390us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 84.390us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 84.390us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 84.390us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 103.824us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 13.000s 1738.581us 1 1 100.00
aes_tl_intg_err 2.000s 324.203us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 324.203us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 141.275us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 84.390us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 84.390us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 191.512us 1 1 100.00
aes_stress 4.000s 364.020us 1 1 100.00
aes_alert_reset 3.000s 141.275us 1 1 100.00
aes_core_fi 3.000s 227.291us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 117.685us 1 1 100.00
aes_stress 4.000s 364.020us 1 1 100.00
aes_core_fi 3.000s 227.291us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 84.390us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 55.090us 1 1 100.00
aes_stress 4.000s 364.020us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 364.020us 1 1 100.00
aes_sideload 3.000s 63.447us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 55.090us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 55.090us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 55.090us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 55.090us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 55.090us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 364.020us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 364.020us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 7.000s 419.660us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 7.000s 419.660us 0 1 0.00
aes_control_fi 2.000s 98.600us 1 1 100.00
aes_cipher_fi 2.000s 64.333us 1 1 100.00
aes_ctr_fi 4.000s 128.389us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 7.000s 419.660us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 7.000s 419.660us 0 1 0.00
aes_control_fi 2.000s 98.600us 1 1 100.00
aes_cipher_fi 2.000s 64.333us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 64.333us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 7.000s 419.660us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 7.000s 419.660us 0 1 0.00
aes_control_fi 2.000s 98.600us 1 1 100.00
aes_ctr_fi 4.000s 128.389us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 7.000s 419.660us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 7.000s 419.660us 0 1 0.00
aes_control_fi 2.000s 98.600us 1 1 100.00
aes_cipher_fi 2.000s 64.333us 1 1 100.00
aes_ctr_fi 4.000s 128.389us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 141.275us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 7.000s 419.660us 0 1 0.00
aes_control_fi 2.000s 98.600us 1 1 100.00
aes_cipher_fi 2.000s 64.333us 1 1 100.00
aes_ctr_fi 4.000s 128.389us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 7.000s 419.660us 0 1 0.00
aes_control_fi 2.000s 98.600us 1 1 100.00
aes_cipher_fi 2.000s 64.333us 1 1 100.00
aes_ctr_fi 4.000s 128.389us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 7.000s 419.660us 0 1 0.00
aes_control_fi 2.000s 98.600us 1 1 100.00
aes_ctr_fi 4.000s 128.389us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 7.000s 419.660us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 7.000s 419.660us 0 1 0.00
aes_control_fi 2.000s 98.600us 1 1 100.00
aes_cipher_fi 2.000s 64.333us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 24.000s 15471.860us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 15575860712113236694389618064080484638061931133338575592824031833445662030071 6720
UVM_INFO @ 68314913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 70289310013937973418098599026941489411767256311175886025359109431723295281790 12267
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (aes_scoreboard.sv:782) scoreboard [scoreboard] # * 1 test run
aes_stress_all 73115518863951843293189718596397358506372292039906341788833644830744887829723 46036
TEST FAILED MESSAGES DID NOT MATCH
0 68 c8 c8 0
1 00 d5 d5 0
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 58502723790362919024899797821268589843544965315978605286470846538782086849024 411
UVM_INFO @ 15471860290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---