Simulation Results: aes/unmasked

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 86.74 %
  • code
  • 89.63 %
  • assert
  • 97.73 %
  • func
  • 72.85 %
  • block
  • 89.40 %
  • line
  • 91.72 %
  • branch
  • 79.91 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 66.665us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 70.085us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 106.588us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 96.505us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 1522.946us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 184.202us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 83.081us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 96.505us 1 1 100.00
aes_csr_aliasing 2.000s 184.202us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 70.085us 1 1 100.00
aes_config_error 2.000s 86.962us 1 1 100.00
aes_stress 3.000s 81.420us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 70.085us 1 1 100.00
aes_config_error 2.000s 86.962us 1 1 100.00
aes_stress 3.000s 81.420us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 81.420us 1 1 100.00
aes_b2b 5.000s 97.020us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 81.420us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 70.085us 1 1 100.00
aes_config_error 2.000s 86.962us 1 1 100.00
aes_stress 3.000s 81.420us 1 1 100.00
aes_alert_reset 4.000s 1323.475us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 67.687us 1 1 100.00
aes_config_error 2.000s 86.962us 1 1 100.00
aes_alert_reset 4.000s 1323.475us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 64.769us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 1655.725us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 1323.475us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 81.420us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 81.420us 1 1 100.00
aes_sideload 3.000s 205.149us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 83.068us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 13.000s 587.906us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 52.694us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 84.891us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 84.891us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 106.588us 1 1 100.00
aes_csr_rw 2.000s 96.505us 1 1 100.00
aes_csr_aliasing 2.000s 184.202us 1 1 100.00
aes_same_csr_outstanding 3.000s 95.429us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 106.588us 1 1 100.00
aes_csr_rw 2.000s 96.505us 1 1 100.00
aes_csr_aliasing 2.000s 184.202us 1 1 100.00
aes_same_csr_outstanding 3.000s 95.429us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 2.000s 28.250us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 3.000s 173.159us 0 1 0.00
aes_control_fi 2.000s 62.857us 1 1 100.00
aes_cipher_fi 2.000s 73.291us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 156.350us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 156.350us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 156.350us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 156.350us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 113.452us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 704.734us 1 1 100.00
aes_tl_intg_err 2.000s 385.052us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 385.052us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 1323.475us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 156.350us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 156.350us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 70.085us 1 1 100.00
aes_stress 3.000s 81.420us 1 1 100.00
aes_alert_reset 4.000s 1323.475us 1 1 100.00
aes_core_fi 3.000s 345.457us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 86.962us 1 1 100.00
aes_stress 3.000s 81.420us 1 1 100.00
aes_core_fi 3.000s 345.457us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 156.350us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 91.832us 1 1 100.00
aes_stress 3.000s 81.420us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 81.420us 1 1 100.00
aes_sideload 3.000s 205.149us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 91.832us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 91.832us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 91.832us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 91.832us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 91.832us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 81.420us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 81.420us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 173.159us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 173.159us 0 1 0.00
aes_control_fi 2.000s 62.857us 1 1 100.00
aes_cipher_fi 2.000s 73.291us 1 1 100.00
aes_ctr_fi 2.000s 58.834us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 173.159us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 173.159us 0 1 0.00
aes_control_fi 2.000s 62.857us 1 1 100.00
aes_cipher_fi 2.000s 73.291us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 73.291us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 173.159us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 173.159us 0 1 0.00
aes_control_fi 2.000s 62.857us 1 1 100.00
aes_ctr_fi 2.000s 58.834us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 173.159us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 173.159us 0 1 0.00
aes_control_fi 2.000s 62.857us 1 1 100.00
aes_cipher_fi 2.000s 73.291us 1 1 100.00
aes_ctr_fi 2.000s 58.834us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 1323.475us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 173.159us 0 1 0.00
aes_control_fi 2.000s 62.857us 1 1 100.00
aes_cipher_fi 2.000s 73.291us 1 1 100.00
aes_ctr_fi 2.000s 58.834us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 173.159us 0 1 0.00
aes_control_fi 2.000s 62.857us 1 1 100.00
aes_cipher_fi 2.000s 73.291us 1 1 100.00
aes_ctr_fi 2.000s 58.834us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 173.159us 0 1 0.00
aes_control_fi 2.000s 62.857us 1 1 100.00
aes_ctr_fi 2.000s 58.834us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 173.159us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 173.159us 0 1 0.00
aes_control_fi 2.000s 62.857us 1 1 100.00
aes_cipher_fi 2.000s 73.291us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 12.940us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 25132778609204179436048032098763359393077368723782897701418453237787346307152 1766
UVM_INFO @ 28250344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 52437873502216461123689616985710621961641016627371409770765646404104585512494 6182
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 4
----| Expected corrupted: 0
UVM_FATAL (aes_scoreboard.sv:782) scoreboard [scoreboard] # * 1 test run
aes_stress_all 97024765526601599468803996834081905407061983196079723862216883625660485189934 38526
TEST FAILED MESSAGES DID NOT MATCH
0 de a6 a6 0
1 00 fa fa 0
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 63863800297558208220326179535764675237032381633762221836896855405594990193162 136
UVM_INFO @ 12939776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---