Simulation Results: alert_handler

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.86 %
  • code
  • 91.79 %
  • assert
  • 98.33 %
  • func
  • 82.46 %
  • line
  • 99.70 %
  • branch
  • 98.47 %
  • cond
  • 92.33 %
  • toggle
  • 91.01 %
  • FSM
  • 77.42 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 8.750s 176.426us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 6.610s 258.107us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 7.680s 116.010us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 122.270s 1252.123us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 50.590s 4113.201us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.290s 34.291us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 7.680s 116.010us 1 1 100.00
alert_handler_csr_aliasing 50.590s 4113.201us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 162.100s 5189.472us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 49.950s 4010.157us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 2018.860s 58741.714us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 34.550s 438.674us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 8.750s 176.426us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 63.510s 5075.720us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 25.990s 603.413us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 320.760s 31763.888us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 2151.280s 49936.481us 1 1 100.00
alert_handler_lpg_stub_clk 3170.930s 73016.929us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1155.360s 17625.819us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 23.930s 467.430us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 4.340s 44.367us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.850s 9.125us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 8.350s 377.910us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 8.350s 377.910us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 6.610s 258.107us 1 1 100.00
alert_handler_csr_rw 7.680s 116.010us 1 1 100.00
alert_handler_csr_aliasing 50.590s 4113.201us 1 1 100.00
alert_handler_same_csr_outstanding 39.980s 3270.609us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 6.610s 258.107us 1 1 100.00
alert_handler_csr_rw 7.680s 116.010us 1 1 100.00
alert_handler_csr_aliasing 50.590s 4113.201us 1 1 100.00
alert_handler_same_csr_outstanding 39.980s 3270.609us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 143.550s 3474.957us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 143.550s 3474.957us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 143.550s 3474.957us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 143.550s 3474.957us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 247.670s 2525.892us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 15.290s 493.721us 1 1 100.00
alert_handler_tl_intg_err 4.270s 40.726us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 4.270s 40.726us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 143.550s 3474.957us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 8.750s 176.426us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 8.750s 176.426us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 8.750s 176.426us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 8.750s 176.426us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 34.550s 438.674us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 2151.280s 49936.481us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 34.550s 438.674us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2018.860s 58741.714us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2018.860s 58741.714us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.290s 493.721us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.290s 493.721us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.290s 493.721us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.290s 493.721us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 15.290s 493.721us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.290s 493.721us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.290s 493.721us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.290s 493.721us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 15.290s 493.721us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 112.680s 1676.592us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 53349906388297130846694417376402875452060386930027707380363101095297297340906 214
UVM_INFO @ 467430284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 103724563525692337920423430770634038113094849452010726836323483242145761985281 122
UVM_INFO @ 1676591661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---