Simulation Results

Simulation Results: chip

02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
70.18 %

code
75.82 %

assert
96.74 %

func
37.98 %

line
93.72 %

branch
93.23 %

cond
88.57 %

toggle
70.24 %

FSM
33.33 %

Validation stages

V1		94.12%
V2		84.79%
V2S		100.00%
V3		52.00%
unmapped		12.50%

16/17 passed

94.12 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				3	3	100.00
	chip_sw_example_rom	105.470s	2274.089us	1	1	100.00
	chip_sw_example_manufacturer	223.810s	2859.360us	1	1	100.00
	chip_sw_example_concurrency	194.630s	3074.607us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	545.040s	12153.394us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	405.290s	8554.551us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	700.320s	10122.187us	1	1	100.00
csr_aliasing				0	1	0.00
	chip_csr_aliasing	10800.145s	0.000us	0	1	0.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	667.250s	11491.949us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				1	2	50.00
	chip_csr_aliasing	10800.145s	0.000us	0	1	0.00
	chip_csr_rw	405.290s	8554.551us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	4.730s	39.490us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	412.150s	4230.256us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	412.150s	4230.256us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	412.150s	4230.256us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	480.440s	4025.432us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	480.440s	4025.432us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	442.570s	3996.470us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	487.740s	4078.451us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	506.200s	4453.367us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	2207.800s	12986.217us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	2144.300s	13432.750us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1026.540s	13054.092us	1	1	100.00

223/263 passed

84.79 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	428.370s	6742.367us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	428.370s	6742.367us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	231.070s	3244.166us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	332.080s	4533.386us	1	1	100.00
chip_sw_sleep_pin_retention				0	1	0.00
	chip_sw_sleep_pin_retention	238.820s	2655.032us	0	1	0.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	687.280s	9655.689us	1	1	100.00
	chip_tap_straps_testunlock0	259.380s	4168.118us	1	1	100.00
	chip_tap_straps_rma	134.750s	2872.704us	1	1	100.00
	chip_tap_straps_prod	122.580s	2182.235us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	541.790s	5139.216us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	541.790s	5139.216us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	829.090s	7191.125us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1084.320s	9746.094us	0	1	0.00
chip_sw_ast_sys_clk_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4321.030s	18988.364us	1	1	100.00
	chip_sw_aes_enc_jitter_en	205.850s	2702.719us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	939.890s	7470.684us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	234.780s	3163.009us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	2009.230s	12634.635us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	267.830s	2976.430us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	476.840s	5020.612us	1	1	100.00
	chip_sw_clkmgr_jitter	191.080s	2717.594us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	231.470s	2950.188us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				1	2	50.00
	chip_sw_sensor_ctrl_alert	598.730s	6536.915us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	190.300s	2152.957us	0	1	0.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	194.360s	2281.989us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				0	1	0.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	190.300s	2152.957us	0	1	0.00
chip_sw_smoketest				16	16	100.00
	chip_sw_aes_smoketest	196.310s	2668.621us	1	1	100.00
	chip_sw_aon_timer_smoketest	241.400s	2999.115us	1	1	100.00
	chip_sw_clkmgr_smoketest	167.460s	2553.432us	1	1	100.00
	chip_sw_csrng_smoketest	244.610s	2730.366us	1	1	100.00
	chip_sw_entropy_src_smoketest	1083.740s	7233.595us	1	1	100.00
	chip_sw_gpio_smoketest	288.320s	3431.985us	1	1	100.00
	chip_sw_hmac_smoketest	330.560s	3132.680us	1	1	100.00
	chip_sw_kmac_smoketest	305.560s	2642.500us	1	1	100.00
	chip_sw_otbn_smoketest	748.260s	5353.795us	1	1	100.00
	chip_sw_pwrmgr_smoketest	289.860s	5264.514us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	308.130s	5826.923us	1	1	100.00
	chip_sw_rv_plic_smoketest	184.020s	2832.433us	1	1	100.00
	chip_sw_rv_timer_smoketest	249.150s	2499.299us	1	1	100.00
	chip_sw_rstmgr_smoketest	218.170s	2428.657us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	199.970s	2315.666us	1	1	100.00
	chip_sw_uart_smoketest	240.780s	2967.231us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	195.710s	2773.276us	1	1	100.00
chip_sw_rom_functests				1	1	100.00
	rom_keymgr_dpe_functest	427.370s	4679.908us	1	1	100.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	20510.620s	127892.976us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3607.710s	15646.246us	1	1	100.00
chip_sw_rom_raw_unlock				1	1	100.00
	rom_raw_unlock	520.480s	10204.672us	1	1	100.00
chip_sw_power_idle_load				1	1	100.00
	chip_sw_power_idle_load	443.120s	4118.264us	1	1	100.00
chip_sw_power_sleep_load				1	1	100.00
	chip_sw_power_sleep_load	332.620s	9752.931us	1	1	100.00
chip_sw_exit_test_unlocked_bootstrap				0	1	0.00
	chip_sw_exit_test_unlocked_bootstrap	13200.139s	0.000us	0	1	0.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	3600.166s	0.000us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	3600.166s	0.000us	0	1	0.00
tl_d_outstanding_access				3	4	75.00
	chip_csr_aliasing	10800.145s	0.000us	0	1	0.00
	chip_same_csr_outstanding	3286.020s	28983.221us	1	1	100.00
	chip_csr_hw_reset	545.040s	12153.394us	1	1	100.00
	chip_csr_rw	405.290s	8554.551us	1	1	100.00
tl_d_partial_access				3	4	75.00
	chip_csr_aliasing	10800.145s	0.000us	0	1	0.00
	chip_same_csr_outstanding	3286.020s	28983.221us	1	1	100.00
	chip_csr_hw_reset	545.040s	12153.394us	1	1	100.00
	chip_csr_rw	405.290s	8554.551us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	49.790s	1485.100us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	4.550s	41.990us	1	1	100.00
	xbar_smoke_large_delays	65.020s	7734.959us	1	1	100.00
	xbar_smoke_slow_rsp	45.030s	4286.714us	1	1	100.00
	xbar_random_zero_delays	17.610s	153.953us	1	1	100.00
	xbar_random_large_delays	149.530s	21634.949us	1	1	100.00
	xbar_random_slow_rsp	205.300s	20397.012us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	21.810s	269.708us	1	1	100.00
	xbar_error_and_unmapped_addr	19.890s	171.745us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	18.500s	215.903us	1	1	100.00
	xbar_error_and_unmapped_addr	19.890s	171.745us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	29.920s	202.863us	1	1	100.00
	xbar_access_same_device_slow_rsp	290.680s	28211.408us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	11.560s	99.483us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	154.210s	5795.909us	1	1	100.00
	xbar_stress_all_with_error	110.560s	4168.515us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	294.820s	7386.589us	1	1	100.00
	xbar_stress_all_with_reset_error	50.160s	192.728us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3607.710s	15646.246us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	3888.530s	35674.828us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	4005.890s	24117.445us	1	1	100.00
rom_e2e_boot_policy_valid				15	15	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	3050.100s	13028.222us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	3964.530s	16054.347us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	4015.320s	16945.741us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	4019.130s	15740.429us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	3896.550s	15359.330us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	2897.180s	10735.370us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	3933.220s	15803.903us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	3970.860s	15905.829us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	3935.050s	16149.568us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	3756.900s	15137.252us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	5154.880s	17308.396us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	6739.790s	25013.290us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	6813.890s	24382.377us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	6955.010s	26139.683us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	6737.010s	23497.159us	1	1	100.00
rom_e2e_sigverify_always				14	15	93.33
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	5887.980s	30637.130us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	6833.420s	36896.987us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	7043.850s	33860.657us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	6732.780s	26911.691us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	6777.560s	35434.264us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	2854.040s	10873.709us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	3682.210s	20778.110us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	3733.210s	22933.614us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	5025.720s	38841.151us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	4166.910s	28028.058us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	3170.300s	15610.334us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	3763.540s	21590.199us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	3972.880s	26888.233us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	3961.450s	21323.302us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	3621.710s	27521.139us	1	1	100.00
rom_e2e_asm_init				5	5	100.00
	rom_e2e_asm_init_test_unlocked0	2863.700s	11007.026us	1	1	100.00
	rom_e2e_asm_init_dev	3905.270s	15616.050us	1	1	100.00
	rom_e2e_asm_init_prod	3884.540s	16577.950us	1	1	100.00
	rom_e2e_asm_init_prod_end	4001.520s	16130.746us	1	1	100.00
	rom_e2e_asm_init_rma	3738.350s	15101.037us	1	1	100.00
rom_e2e_keymgr_dpe_init				2	3	66.67
	rom_e2e_keymgr_dpe_init_rom_ext_meas	7395.060s	28972.680us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_no_meas	7329.850s	30640.315us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas	3755.240s	17262.443us	0	1	0.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3774.990s	15900.273us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3395.050s	34568.556us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3395.050s	34568.556us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	201.360s	2980.556us	1	1	100.00
	chip_sw_aes_enc_jitter_en	205.850s	2702.719us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	197.470s	2329.548us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	190.180s	2758.588us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	1588.850s	9731.270us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	204.790s	2700.552us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	388.810s	4686.427us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	473.430s	4790.457us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	514.030s	4519.644us	1	1	100.00
	chip_plic_all_irqs_10	377.620s	3508.974us	1	1	100.00
	chip_plic_all_irqs_20	490.510s	3991.520us	1	1	100.00
chip_sw_alert_handler_entropy				0	1	0.00
	chip_sw_alert_handler_entropy	264.070s	2683.816us	0	1	0.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1047.240s	8459.422us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	460.210s	4556.590us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	242.120s	2447.714us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	210.600s	2827.151us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1395.210s	8708.122us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1251.000s	7096.013us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	934.580s	7949.989us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	11724.980s	255805.539us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	292.890s	3302.086us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	289.860s	5264.514us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	292.890s	3302.086us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	535.810s	7453.944us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	535.810s	7453.944us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	457.250s	6701.576us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	449.740s	4962.584us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	811.310s	6052.747us	1	1	100.00
	chip_sw_aes_idle	190.180s	2758.588us	1	1	100.00
	chip_sw_hmac_enc_idle	296.680s	3156.899us	1	1	100.00
	chip_sw_kmac_idle	208.260s	2622.965us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	385.860s	3801.579us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	336.600s	4024.723us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	415.880s	4095.360us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	284.790s	3675.156us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	985.090s	10082.262us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	451.000s	3764.110us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	552.470s	4894.241us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	537.490s	3979.410us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	523.870s	4792.144us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	479.590s	3781.277us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	480.920s	4652.549us	1	1	100.00
	chip_sw_ast_clk_outputs	829.090s	7191.125us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	974.040s	13973.064us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	537.490s	3979.410us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	523.870s	4792.144us	1	1	100.00
chip_sw_clkmgr_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4321.030s	18988.364us	1	1	100.00
	chip_sw_aes_enc_jitter_en	205.850s	2702.719us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	939.890s	7470.684us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	234.780s	3163.009us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	2009.230s	12634.635us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	267.830s	2976.430us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	476.840s	5020.612us	1	1	100.00
	chip_sw_clkmgr_jitter	191.080s	2717.594us	1	1	100.00
chip_sw_clkmgr_extended_range				8	8	100.00
	chip_sw_clkmgr_jitter_reduced_freq	194.870s	2594.079us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4475.730s	25127.824us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	226.920s	3096.441us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	190.800s	2666.274us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	1014.290s	8326.690us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	271.250s	3493.514us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	493.690s	4780.556us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	2398.140s	15261.215us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	829.090s	7191.125us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				0	1	0.00
	chip_sw_clkmgr_sleep_frequency	416.620s	4517.840us	0	1	0.00
chip_sw_clkmgr_reset_frequency				0	1	0.00
	chip_sw_clkmgr_reset_frequency	578.530s	7297.757us	0	1	0.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	473.430s	4790.457us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1395.210s	8708.122us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	1041.190s	6560.846us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	321.920s	4470.869us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	781.540s	8637.253us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	192.260s	2943.692us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	3719.640s	17082.845us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	167.500s	2448.011us	1	1	100.00
	chip_sw_edn_entropy_reqs	695.320s	4935.350us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	167.500s	2448.011us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	1041.190s	6560.846us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	202.480s	2598.967us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	249.760s	2623.586us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	234.780s	3163.009us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	296.680s	3156.899us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	2032.300s	11679.462us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	2276.240s	12010.160us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	554.170s	5019.415us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	464.280s	4490.916us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	543.900s	4258.522us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	375.560s	3774.628us	1	1	100.00
chip_sw_keymgr_dpe_key_derivation				2	2	100.00
	chip_sw_keymgr_dpe_key_derivation	2073.270s	12583.737us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	2009.230s	12634.635us	1	1	100.00
chip_sw_keymgr_dpe_sideload_kmac				1	1	100.00
	chip_sw_keymgr_dpe_sideload_kmac	2097.670s	11817.087us	1	1	100.00
chip_sw_keymgr_dpe_sideload_aes				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	1588.850s	9731.270us	1	1	100.00
chip_sw_keymgr_dpe_sideload_otbn				0	1	0.00
	chip_sw_keymgr_dpe_sideload_otbn	3600.162s	0.000us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	186.020s	2749.009us	1	1	100.00
	chip_sw_kmac_mode_kmac	198.850s	2592.204us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	267.830s	2976.430us	1	1	100.00
chip_sw_kmac_app_keymgr_dpe				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	2073.270s	12583.737us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	954.890s	15357.249us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	371.520s	5206.206us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	787.900s	5338.339us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	208.260s	2622.965us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	388.810s	4686.427us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	687.280s	9655.689us	1	1	100.00
	chip_tap_straps_rma	134.750s	2872.704us	1	1	100.00
	chip_tap_straps_prod	122.580s	2182.235us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	258.770s	2738.693us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	954.890s	15357.249us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	954.890s	15357.249us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	954.890s	15357.249us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_prod	1349.320s	9171.220us	1	1	100.00
chip_sw_lc_ctrl_broadcast				18	21	85.71
	chip_sw_rram_rma_unlocked	427.040s	10010.180us	0	1	0.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	277.350s	3734.950us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	759.860s	6130.359us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	766.840s	6284.199us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	718.070s	5428.767us	0	1	0.00
	chip_sw_lc_ctrl_transition	954.890s	15357.249us	1	1	100.00
	chip_sw_rram_ctrl_lc_rw_en	379.200s	4366.043us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	2073.270s	12583.737us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	826.660s	17428.234us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	563.720s	7409.341us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	974.040s	13973.064us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	451.000s	3764.110us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	552.470s	4894.241us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	537.490s	3979.410us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	523.870s	4792.144us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	479.590s	3781.277us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	480.920s	4652.549us	1	1	100.00
	chip_tap_straps_dev	687.280s	9655.689us	1	1	100.00
	chip_tap_straps_rma	134.750s	2872.704us	1	1	100.00
	chip_tap_straps_prod	122.580s	2182.235us	1	1	100.00
	chip_rv_dm_lc_disabled	78.200s	2914.184us	0	1	0.00
chip_lc_scrap				2	4	50.00
	chip_sw_lc_ctrl_rma_to_scrap	348.370s	5215.300us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	543.260s	11520.399us	0	1	0.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	415.410s	7828.543us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	449.810s	7683.972us	0	1	0.00
chip_lc_test_locked				0	2	0.00
	chip_sw_lc_walkthrough_testunlocks	3600.169s	0.000us	0	1	0.00
	chip_rv_dm_lc_disabled	78.200s	2914.184us	0	1	0.00
chip_sw_lc_walkthrough				1	5	20.00
	chip_sw_lc_walkthrough_dev	1475.040s	19637.763us	0	1	0.00
	chip_sw_lc_walkthrough_prod	1377.200s	18886.980us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	1416.260s	19799.358us	1	1	100.00
	chip_sw_lc_walkthrough_rma	1047.830s	14325.245us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	3600.169s	0.000us	0	1	0.00
chip_sw_lc_ctrl_volatile_raw_unlock				3	3	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock	278.310s	5655.767us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	199.110s	3991.800us	1	1	100.00
	rom_volatile_raw_unlock	246.690s	5660.577us	1	1	100.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	4110.820s	16761.688us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4321.030s	18988.364us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	811.310s	6052.747us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	811.310s	6052.747us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	811.310s	6052.747us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	421.990s	3530.556us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	954.890s	15357.249us	1	1	100.00
chip_sw_otp_ctrl_keys				3	4	75.00
	chip_sw_otbn_mem_scramble	421.990s	3530.556us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	2073.270s	12583.737us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	504.980s	4820.701us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	3600.191s	0.000us	0	1	0.00
chip_sw_otp_ctrl_entropy				3	4	75.00
	chip_sw_otbn_mem_scramble	421.990s	3530.556us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	2073.270s	12583.737us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	504.980s	4820.701us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	3600.191s	0.000us	0	1	0.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	954.890s	15357.249us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	520.110s	5571.230us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	258.770s	2738.693us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				4	5	80.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	277.350s	3734.950us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	759.860s	6130.359us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	766.840s	6284.199us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	718.070s	5428.767us	0	1	0.00
	chip_sw_lc_ctrl_transition	954.890s	15357.249us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	1089.980s	7279.836us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	359.500s	7448.969us	1	1	100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	185.380s	2634.612us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	209.440s	2821.584us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_por_reset	441.710s	7928.371us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_por_reset	426.070s	4530.398us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	820.220s	19820.608us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				2	2	100.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	1338.390s	13134.256us	1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	535.810s	7453.944us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	269.960s	4609.028us	0	1	0.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	440.270s	4864.414us	1	1	100.00
chip_sw_pwrmgr_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	359.500s	7448.969us	1	1	100.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	314.530s	4233.585us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	525.930s	8515.496us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	434.840s	5970.601us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	195.380s	3069.604us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	361.450s	6616.755us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	764.330s	6221.263us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1002.320s	9077.059us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1885.000s	25019.946us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	227.470s	2851.005us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	473.430s	4790.457us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	826.660s	17428.234us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	826.660s	17428.234us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	1002.320s	9077.059us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	361.450s	6616.755us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	440.270s	4864.414us	1	1	100.00
	chip_sw_pwrmgr_smoketest	289.860s	5264.514us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	416.010s	4075.121us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	618.320s	6205.032us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	299.460s	3823.494us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1047.240s	8459.422us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	266.290s	3156.058us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	473.430s	4790.457us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1251.000s	7096.013us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	624.720s	4723.115us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	575.640s	4578.658us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	268.310s	2823.303us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				0	1	0.00
	chip_sw_rv_core_ibex_icache_invalidate	3600.191s	0.000us	0	1	0.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	618.320s	6205.032us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	618.320s	6205.032us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	252.770s	2975.752us	1	1	100.00
chip_jtag_csr_rw				0	1	0.00
	chip_jtag_csr_rw	116.160s	2601.775us	0	1	0.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	1275.950s	20818.805us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	416.010s	4075.121us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	232.440s	3175.839us	0	1	0.00
chip_rv_dm_access_after_wakeup				0	1	0.00
	chip_sw_rv_dm_access_after_wakeup	226.360s	3139.035us	0	1	0.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	134.750s	2872.704us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	78.200s	2914.184us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	514.030s	4519.644us	1	1	100.00
	chip_plic_all_irqs_10	377.620s	3508.974us	1	1	100.00
	chip_plic_all_irqs_20	490.510s	3991.520us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	259.930s	3139.219us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	287.830s	2805.798us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3607.710s	15646.246us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	521.830s	6384.860us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	325.260s	3430.033us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	253.780s	2911.121us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	221.780s	2423.796us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	504.980s	4820.701us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	476.840s	5020.612us	1	1	100.00
chip_sw_sleep_sram_ret_contents				0	2	0.00
	chip_sw_sleep_sram_ret_contents_no_scramble	176.750s	2286.596us	0	1	0.00
	chip_sw_sleep_sram_ret_contents_scramble	251.650s	2839.222us	0	1	0.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	563.720s	7409.341us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	473.430s	4790.457us	1	1	100.00
	chip_sw_data_integrity_escalation	541.790s	5139.216us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	764.330s	6221.263us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1261.730s	23624.549us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	232.830s	2705.015us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	345.910s	3542.653us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	448.300s	4358.147us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1261.730s	23624.549us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1261.730s	23624.549us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	3084.900s	20360.532us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	3084.900s	20360.532us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	360.660s	5612.577us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3395.050s	34568.556us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	222.870s	2497.991us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	176.850s	2362.662us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	319.670s	3412.390us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	350.290s	3393.321us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	988.440s	8235.454us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5999.020s	32158.035us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	2173.990s	12689.161us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	237.450s	3219.318us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	269.810s	2707.798us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	189.080s	2805.895us	1	1	100.00

13/25 passed

52.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	13092.790s	72549.293us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1426.390s	6430.894us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	88.980s	2021.699us	0	1	0.00
	rom_e2e_jtag_debug_dev	87.370s	1925.304us	0	1	0.00
	rom_e2e_jtag_debug_rma	96.460s	2272.401us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	341.540s	4133.274us	0	1	0.00
	rom_e2e_jtag_inject_dev	105.930s	2144.469us	0	1	0.00
	rom_e2e_jtag_inject_rma	90.650s	1942.991us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	50.976s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	280.340s	3081.375us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	357.270s	2900.023us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	809.350s	4829.626us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1323.250s	7810.604us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	327.760s	2478.240us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	252.080s	2960.542us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				0	1	0.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	409.790s	5514.119us	0	1	0.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	420.390s	4573.465us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1002.320s	9077.059us	1	1	100.00
chip_sw_rom_ctrl_digests				1	1	100.00
	chip_sw_kmac_app_rom	371.520s	5206.206us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	88.980s	2021.699us	0	1	0.00
	rom_e2e_jtag_debug_dev	87.370s	1925.304us	0	1	0.00
	rom_e2e_jtag_debug_rma	96.460s	2272.401us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				0	1	0.00
	chip_sw_rv_dm_access_after_escalation_reset	262.230s	3597.828us	0	1	0.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	473.430s	4790.457us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	6094.860s	37521.772us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	6094.860s	37521.772us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				0	1	0.00
	chip_sw_spi_device_pinmux_sleep_retention	218.530s	3302.142us	0	1	0.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	480.440s	4025.432us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3469.080s	19109.505us	1	1	100.00

unmapped

1/8 passed

12.50 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	8	12.50
	chip_sw_rstmgr_rst_cnsty_escalation	51.600s	10.120us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	97.740s	2370.277us	0	1	0.00
	chip_sw_otp_ctrl_descrambling	318.160s	2936.542us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	229.710s	2891.299us	0	1	0.00
	chip_sw_pwrmgr_sleep_wake_5_bug	12.217s	0.000us	0	1	0.00
	ate_bootstrap_flash_erase	694.090s	10010.140us	0	1	0.00
	ate_bootstrap_one_frame	10800.143s	0.000us	0	1	0.00
	ate_bootstrap_disjoint	10800.139s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error				13 test runs
	chip_sw_sleep_pin_retention	35220557873021610322303680251264257480885633981478825153984214357571966416971	379	UVM_INFO @ 2655.032448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_spi_device_pinmux_sleep_retention	106716095909933234545703376232632951848939095496334150812291385141075432904561	374	UVM_INFO @ 3302.141646 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	40117397801801052028014040688114763483770582479072976621596047679456249554565	392	UVM_INFO @ 6616.754572 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	35259421145706501355923498517556266861677832926521737532933206450351815659889	377	UVM_INFO @ 4609.027956 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_por_reset	57121224637866845394137754275882303314552371634742656583736890140503647697386	388	UVM_INFO @ 4530.397972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_no_scramble	14069580310882415906275389923117644710151067020357432413578976470339120039491	377	UVM_INFO @ 2286.596096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_scramble	36124848156791059699417180168054292699620712574168968416527657570391763836102	381	UVM_INFO @ 2839.221852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	93125737001304915965664910540612587536152252512494703465289014332673547231829	372	UVM_INFO @ 2152.956792 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_clkmgr_sleep_frequency	57160156148258700543167074259031799541240092956886608886973714877969068452765	407	UVM_INFO @ 4517.840404 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	87382915644518422318818929947465039155271269037706645893201629028207113727271	374	UVM_INFO @ 2821.584388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_lowpower_cancel	53332308276128637974030916926840342101605838842367753107797411742507232000738	372	UVM_INFO @ 2891.298830 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_wake_ups	96501862448605785184383210014567397073656421838196897807835798083554429837406	373	UVM_INFO @ 2634.611640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_rv_dm_access_after_wakeup	71724526437309213560254719980456932304979238574559228060069386933585427861392	390	UVM_INFO @ 3139.035024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				8 test runs
	chip_csr_aliasing	81663484656950957571779264464294073205492836475736563133027439600949108765911	None
	chip_sw_exit_test_unlocked_bootstrap	77155903185515912065362049382228569232192198680984364630264864780914483259262	None
	chip_sw_lc_walkthrough_testunlocks	35584884869395663221505395981473333504755810046944816817243538587342006184651	None
	chip_sw_keymgr_dpe_sideload_otbn	85510446573217226980437788496996716525008429051626096174246933406282729806730	None
	chip_tl_errors	82289119303411002316996959256481878370482917912209180826265016262615361459622	None
	chip_sw_rv_core_ibex_icache_invalidate	30978191156318233893566233791149879266501240041290049808693523602192309104266	None
	ate_bootstrap_one_frame	24543311087087196336715427851231017767261759014921672973911418132499882214908	None
	ate_bootstrap_disjoint	16106373528735772087811372866220139972932519343879799479721233131357601946471	None
Error-[NOA] Null object access				5 test runs
	chip_sw_otp_ctrl_rot_auth_config	32664701987476133408351171985206974412199738886219750169247004419135228629562	379	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	92925348115166687523008993941291241494292904526250555654436767854143960175284	403	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	44370549808856254990524515533168992580246900107688863119326243972712920199961	386	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	97296037474662871585619162558073127515053481113627657555035693481449480669405	381	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	80395511724036814876520147009459905530948639763797245341256827054245919985349	381	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	87761461563864125817806937237578402993325378825992375914057481054316764149644	433	UVM_INFO @ 19637.762860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	39101229097707111834118070693919715532462476446042481980699461999574765253242	433	UVM_INFO @ 18886.980060 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	93239408334386577212920176912467063546047750330443296745094152257557906887783	405	UVM_INFO @ 14325.244766 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:604) [debugger] Check failed pc == exp_addr (* [] vs [*])				3 test runs
	rom_e2e_jtag_debug_test_unlocked0	3587116034299408652607999943757332648323931322159122814952311639772215384140	359	UVM_INFO @ 2021.699500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_dev	112332987708391202970147830091475566034375526951856531201515270038553598909583	359	UVM_INFO @ 1925.304500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_rma	28303642993653500620534567516234481949622300928517091815068790597436111039254	359	UVM_INFO @ 2272.400500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl				2 test runs
	chip_sw_lc_ctrl_raw_to_scrap	377632194844322076930113119028367575770469003147088299333706636227587052396	375	UVM_INFO @ 11520.399343 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_ctrl_rand_to_scrap	2113268994895359293011843185715610569679086642860547850026482815820496540448	375	UVM_INFO @ 7683.972000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				2 test runs
	chip_sw_pwrmgr_sleep_power_glitch_reset	102446906742730802712463104413379243381054862892690767512310094823596981466708	377	UVM_ERROR @ 3069.604270 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3069.604270 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	84629333879078662513221192962759983792283006042957896016745948705408365629100	393	UVM_ERROR @ 8515.496440 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 8515.496440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error				2 test runs
	chip_sw_alert_handler_lpg_sleep_mode_pings	96315898789003246381611355800708910943889028494686345810922107058386362929331	374	UVM_INFO @ 2827.150616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_alert_handler_entropy	72208657405776594970019722718948058767156212079425039020118437985679656375493	496	UVM_INFO @ 2683.815722 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				2 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	26287127069920298555382202381738467042718371109666117324162747075297554542542	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	6609182478971331797498548789026401102084849617736472771009202773799616373411	None	Another command (pid=423660) is running. Waiting for it to complete on the server (server_pid=217206)... Another command (pid=419646) is running. Waiting for it to complete on the server (server_pid=217206)... Another command (pid=460108) is running. Waiting for it to complete on the server (server_pid=217206)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Offending '(pend_req[h2d.a_source].pend == *)'				2 test runs
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	82431298730022970495920040463632735732712386656307477292498032097991164788643	406	UVM_ERROR @ 28028.058402 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M UVM_INFO @ 28028.058402 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas	27705049164000014817972696716067234919775887948604816421439528670505736285024	386	UVM_ERROR @ 17262.443430 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M UVM_INFO @ 17262.443430 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	100146619277678038118925156419569534929006434912643140734909728114062600934463	365	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch				1 test run
	chip_sw_spi_device_pass_through_collision	104293274114211967541050339996150740296821462698663308052108650386301340687102	393	host_rsp: ------------------------------------------------------------------------- Name Type Size Value -------------------------------------------------------------------------
UVM_FATAL @ * us: (chip_sw_rram_rma_unlocked_vseq.sv:162) [chip_sw_rram_rma_unlocked_vseq] wait timeout occurred!				1 test run
	chip_sw_rram_rma_unlocked	15551289486152633816693934652340612852276899370850793484628383971975657144035	337	UVM_INFO @ 10010.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	20350836193641975883205568249917629531867319204477867648217710285194334784143	404	UVM_INFO @ 5428.766945 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(buf_intg_err == '0)'				1 test run
	chip_sw_otp_ctrl_escalation	6382981652541154718106445718464663399590125922057344633589847447585233930080	380	UVM_ERROR @ 2960.542264 us: (rram_phy_rd.sv:697) [ASSERT FAILED] IntgError UVM_INFO @ 2960.542264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	71878655297622090344128812011919491470704800400173534374285356181743938492363	396	UVM_INFO @ 34568.555724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:370)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	73327234742647223081501172828924728959588311089938866647710114927381062523659	371	UVM_INFO @ 2700.551880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	54411437912964949661592389999402661226486401047601762799793795764716500777719	373	UVM_INFO @ 2447.713844 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_hmac_multistream	74314843405343844348264797030352616907705884586207348010404900544392048813931	429	UVM_INFO @ 12010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state.				1 test run
	chip_sw_clkmgr_reset_frequency	80796613191321611518309907967485853189287583357644184237223938694590238287581	400	UVM_INFO @ 7297.756912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	18331377033727184068326164062755906809705409666168274669801070207900655948600	407	UVM_INFO @ 3081.375272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_riscv_driver.sv:208) driver [driver] Could not activate RV_DM after * attempts!				1 test run
	chip_jtag_csr_rw	54131550088053763605047718166748552261416035063073793746487046381294165167511	5365	UVM_INFO @ 2601.774888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: *				1 test run
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	91131135923150596791052403311472429307771911022108862658682582939599139805619	380	UVM_INFO @ 5514.119288 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rv_jtag_o == '0)'				1 test run
	chip_sw_rv_dm_access_after_escalation_reset	96846293862979608124885245686187437721381038710905836580397109109072291920186	387	UVM_ERROR @ 3597.827562 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A UVM_INFO @ 3597.827562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_rv_dm_lc_disabled_vseq.sv:154) [chip_rv_dm_lc_disabled_vseq] Check failed rdata == exp_data (* [] vs []) RV_DM sbaddress read back check failed, got , expected				1 test run
	chip_rv_dm_lc_disabled	43203150048361776993966885011176728254579590908718643046765643415736449391910	300	UVM_INFO @ 2914.184181 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	77111780629252198960233603588264820152022550311792989663521791231401007261866	391	UVM_INFO @ 9746.093558 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	52256059197834109717794242581921615733942556687865517752660072044345528041280	339	UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---