Simulation Results: clkmgr

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 93.60 %
  • code
  • 98.24 %
  • assert
  • 95.76 %
  • func
  • 86.79 %
  • line
  • 99.02 %
  • branch
  • 98.59 %
  • cond
  • 94.40 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.260s 78.742us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.380s 120.274us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.170s 52.932us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 5.940s 711.505us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.200s 42.111us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 2.220s 353.387us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.170s 52.932us 1 1 100.00
clkmgr_csr_aliasing 1.200s 42.111us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.110s 49.031us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.630s 124.309us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.270s 42.482us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.940s 19.496us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.260s 78.742us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 9.070s 1615.560us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 6.460s 742.328us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 9.070s 1615.560us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 2.450s 488.422us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.060s 18.234us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 9.040s 2513.618us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 9.040s 2513.618us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 1.380s 120.274us 1 1 100.00
clkmgr_csr_rw 1.170s 52.932us 1 1 100.00
clkmgr_csr_aliasing 1.200s 42.111us 1 1 100.00
clkmgr_same_csr_outstanding 1.800s 98.403us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 1.380s 120.274us 1 1 100.00
clkmgr_csr_rw 1.170s 52.932us 1 1 100.00
clkmgr_csr_aliasing 1.200s 42.111us 1 1 100.00
clkmgr_same_csr_outstanding 1.800s 98.403us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 57.920s 10037.798us 0 1 0.00
clkmgr_tl_intg_err 3.560s 246.083us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.510s 52.814us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.510s 52.814us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.510s 52.814us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.510s 52.814us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 3.010s 126.076us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 3.560s 246.083us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 9.070s 1615.560us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 6.460s 742.328us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.510s 52.814us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.510s 45.298us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.260s 77.433us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.200s 31.769us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.330s 33.078us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.580s 109.479us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.170s 52.932us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 57.920s 10037.798us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.170s 52.932us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.170s 52.932us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 57.920s 10037.798us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.500s 326.500us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 50.740s 10193.502us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1087) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 22574539606934360733728487550917256923981326985830460055307654204310387756564 106
UVM_INFO @ 10037797777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---