Simulation Results: edn/edn0

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 85.93 %
  • code
  • 80.29 %
  • assert
  • 96.75 %
  • func
  • 80.75 %
  • line
  • 97.23 %
  • branch
  • 90.79 %
  • cond
  • 86.42 %
  • toggle
  • 78.08 %
  • FSM
  • 48.92 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.470s 22.820us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.270s 90.652us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.200s 78.251us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.580s 47.588us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.160s 106.350us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.060s 32.558us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.200s 78.251us 1 1 100.00
edn_csr_aliasing 1.160s 106.350us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.030s 44.801us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.030s 44.801us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.030s 44.801us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.260s 21.779us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.660s 89.344us 1 1 100.00
errs 1 1 100.00
edn_err 1.260s 19.104us 1 1 100.00
disable 2 2 100.00
edn_disable 1.260s 41.959us 1 1 100.00
edn_disable_auto_req_mode 1.760s 48.318us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.610s 75.579us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.270s 52.431us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.320s 48.694us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.340s 147.179us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.340s 147.179us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.270s 90.652us 1 1 100.00
edn_csr_rw 1.200s 78.251us 1 1 100.00
edn_csr_aliasing 1.160s 106.350us 1 1 100.00
edn_same_csr_outstanding 1.400s 17.302us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.270s 90.652us 1 1 100.00
edn_csr_rw 1.200s 78.251us 1 1 100.00
edn_csr_aliasing 1.160s 106.350us 1 1 100.00
edn_same_csr_outstanding 1.400s 17.302us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 10.100s 2033.130us 1 1 100.00
edn_tl_intg_err 3.130s 154.256us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.370s 24.049us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.660s 89.344us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.100s 2033.130us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.100s 2033.130us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 10.100s 2033.130us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 10.100s 2033.130us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.660s 89.344us 1 1 100.00
edn_sec_cm 10.100s 2033.130us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.660s 89.344us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.130s 154.256us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 84.760s 3203.659us 1 1 100.00