Simulation Results: edn/edn1

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 87.58 %
  • code
  • 83.62 %
  • assert
  • 98.44 %
  • func
  • 80.67 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 88.46 %
  • toggle
  • 93.84 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.290s 20.018us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.090s 52.737us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.170s 31.120us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.570s 266.838us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.360s 15.599us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.330s 69.086us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.170s 31.120us 1 1 100.00
edn_csr_aliasing 1.360s 15.599us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.470s 98.522us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.470s 98.522us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.470s 98.522us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.200s 22.968us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.460s 80.181us 1 1 100.00
errs 1 1 100.00
edn_err 1.360s 24.382us 1 1 100.00
disable 2 2 100.00
edn_disable 1.170s 20.579us 1 1 100.00
edn_disable_auto_req_mode 1.380s 71.633us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.260s 88.925us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.100s 30.400us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.280s 52.932us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.070s 71.572us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.070s 71.572us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.090s 52.737us 1 1 100.00
edn_csr_rw 1.170s 31.120us 1 1 100.00
edn_csr_aliasing 1.360s 15.599us 1 1 100.00
edn_same_csr_outstanding 1.230s 100.478us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.090s 52.737us 1 1 100.00
edn_csr_rw 1.170s 31.120us 1 1 100.00
edn_csr_aliasing 1.360s 15.599us 1 1 100.00
edn_same_csr_outstanding 1.230s 100.478us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.850s 308.604us 1 1 100.00
edn_tl_intg_err 2.610s 253.977us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.170s 59.199us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.460s 80.181us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.850s 308.604us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.850s 308.604us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.850s 308.604us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.850s 308.604us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.460s 80.181us 1 1 100.00
edn_sec_cm 2.850s 308.604us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.460s 80.181us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.610s 253.977us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 13.510s 1083.882us 1 1 100.00