Simulation Results: hmac

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 75.07 %
  • code
  • 86.11 %
  • assert
  • 97.60 %
  • func
  • 41.49 %
  • line
  • 99.54 %
  • branch
  • 98.21 %
  • cond
  • 95.46 %
  • toggle
  • 46.17 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 7.280s 748.476us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.020s 22.159us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.080s 24.124us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 15.360s 464.772us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 1.980s 750.494us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.100s 15.248us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.080s 24.124us 1 1 100.00
hmac_csr_aliasing 1.980s 750.494us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 1.140s 73.148us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 58.470s 12998.066us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 13.310s 536.909us 1 1 100.00
hmac_test_sha384_vectors 444.280s 19383.007us 1 1 100.00
hmac_test_sha512_vectors 411.440s 17051.936us 1 1 100.00
hmac_test_hmac256_vectors 14.580s 473.091us 1 1 100.00
hmac_test_hmac384_vectors 9.630s 875.153us 1 1 100.00
hmac_test_hmac512_vectors 12.770s 4276.372us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 27.030s 10940.150us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 338.220s 27214.173us 1 1 100.00
error 1 1 100.00
hmac_error 104.880s 18090.463us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 127.510s 15999.039us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 7.280s 748.476us 1 1 100.00
hmac_long_msg 1.140s 73.148us 1 1 100.00
hmac_back_pressure 58.470s 12998.066us 1 1 100.00
hmac_datapath_stress 338.220s 27214.173us 1 1 100.00
hmac_burst_wr 27.030s 10940.150us 1 1 100.00
hmac_stress_all 214.980s 22595.240us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 7.280s 748.476us 1 1 100.00
hmac_long_msg 1.140s 73.148us 1 1 100.00
hmac_back_pressure 58.470s 12998.066us 1 1 100.00
hmac_datapath_stress 338.220s 27214.173us 1 1 100.00
hmac_wipe_secret 127.510s 15999.039us 1 1 100.00
hmac_test_sha256_vectors 13.310s 536.909us 1 1 100.00
hmac_test_sha384_vectors 444.280s 19383.007us 1 1 100.00
hmac_test_sha512_vectors 411.440s 17051.936us 1 1 100.00
hmac_test_hmac256_vectors 14.580s 473.091us 1 1 100.00
hmac_test_hmac384_vectors 9.630s 875.153us 1 1 100.00
hmac_test_hmac512_vectors 12.770s 4276.372us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 7.280s 748.476us 1 1 100.00
hmac_long_msg 1.140s 73.148us 1 1 100.00
hmac_back_pressure 58.470s 12998.066us 1 1 100.00
hmac_datapath_stress 338.220s 27214.173us 1 1 100.00
hmac_burst_wr 27.030s 10940.150us 1 1 100.00
hmac_error 104.880s 18090.463us 1 1 100.00
hmac_wipe_secret 127.510s 15999.039us 1 1 100.00
hmac_test_sha256_vectors 13.310s 536.909us 1 1 100.00
hmac_test_sha384_vectors 444.280s 19383.007us 1 1 100.00
hmac_test_sha512_vectors 411.440s 17051.936us 1 1 100.00
hmac_test_hmac256_vectors 14.580s 473.091us 1 1 100.00
hmac_test_hmac384_vectors 9.630s 875.153us 1 1 100.00
hmac_test_hmac512_vectors 12.770s 4276.372us 1 1 100.00
hmac_stress_all 214.980s 22595.240us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 214.980s 22595.240us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.890s 27.048us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.920s 13.430us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.440s 610.481us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.440s 610.481us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.020s 22.159us 1 1 100.00
hmac_csr_rw 1.080s 24.124us 1 1 100.00
hmac_csr_aliasing 1.980s 750.494us 1 1 100.00
hmac_same_csr_outstanding 1.740s 362.210us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.020s 22.159us 1 1 100.00
hmac_csr_rw 1.080s 24.124us 1 1 100.00
hmac_csr_aliasing 1.980s 750.494us 1 1 100.00
hmac_same_csr_outstanding 1.740s 362.210us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.280s 84.398us 1 1 100.00
hmac_tl_intg_err 3.240s 2606.603us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.240s 2606.603us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 7.280s 748.476us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.730s 148.142us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 19.310s 2504.096us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.300s 31.089us 1 1 100.00