Simulation Results: i2c

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 85.69 %
  • code
  • 78.65 %
  • assert
  • 97.25 %
  • func
  • 81.18 %
  • line
  • 96.72 %
  • branch
  • 92.62 %
  • cond
  • 84.63 %
  • toggle
  • 74.04 %
  • FSM
  • 45.24 %
Validation stages
V1
100.00%
V2
85.37%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 49.320s 6059.669us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 9.310s 976.772us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 1.120s 291.657us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 1.140s 100.833us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 2.610s 172.546us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.090s 66.459us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.090s 24.636us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 1.140s 100.833us 1 1 100.00
i2c_csr_aliasing 1.090s 66.459us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.090s 15.703us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 228.490s 9527.719us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 12.600s 1769.838us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.910s 106.499us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 161.840s 3976.627us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 99.100s 9376.450us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.040s 97.795us 1 1 100.00
i2c_host_fifo_fmt_empty 6.030s 1493.016us 1 1 100.00
i2c_host_fifo_reset_rx 6.850s 172.919us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 146.110s 12221.747us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 21.320s 513.538us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 1.630s 103.178us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 3.360s 1940.901us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 106.860s 23406.961us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 5.150s 1071.157us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 54.340s 1486.921us 1 1 100.00
i2c_target_intr_smoke 4.480s 1301.029us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.290s 410.249us 1 1 100.00
i2c_target_fifo_reset_tx 1.360s 202.355us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 796.990s 52800.686us 1 1 100.00
i2c_target_stress_rd 54.340s 1486.921us 1 1 100.00
i2c_target_intr_stress_wr 24.290s 14945.051us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 8.240s 5816.220us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 89.020s 3827.157us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.910s 862.417us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 4.190s 10592.324us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.810s 453.829us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.110s 176.433us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 12.600s 1769.838us 1 1 100.00
i2c_host_perf_precise 1.450s 243.962us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 21.320s 513.538us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 1.830s 56.060us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 2.790s 2195.994us 1 1 100.00
i2c_target_nack_acqfull_addr 3.440s 2008.067us 1 1 100.00
i2c_target_nack_txstretch 2.170s 396.935us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 6.060s 545.837us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 2.480s 1106.725us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.960s 28.553us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.950s 16.998us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.800s 68.996us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.800s 68.996us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
i2c_csr_hw_reset 1.120s 291.657us 1 1 100.00
i2c_csr_rw 1.140s 100.833us 1 1 100.00
i2c_csr_aliasing 1.090s 66.459us 1 1 100.00
i2c_same_csr_outstanding 1.510s 86.733us 0 1 0.00
tl_d_partial_access 3 4 75.00
i2c_csr_hw_reset 1.120s 291.657us 1 1 100.00
i2c_csr_rw 1.140s 100.833us 1 1 100.00
i2c_csr_aliasing 1.090s 66.459us 1 1 100.00
i2c_same_csr_outstanding 1.510s 86.733us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 2.070s 144.841us 1 1 100.00
i2c_sec_cm 1.320s 294.193us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 2.070s 144.841us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 6.750s 577.911us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.970s 19.529us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 29.540s 25977.388us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 3 test runs
i2c_host_error_intr 91750787382294859703178199154636973007827363681049831788120391045589704228816 86
UVM_INFO @ 15703052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 31053820959253753295056926826715505490956489667813595100570028751444127993756 123
UVM_INFO @ 9527718873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 56777336553320497139387515597018051524101938977010703155876183476047621329624 146
UVM_INFO @ 25977388094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 74217564023948235434156760596245409806218555958666644065222120013359442856117 90
UVM_INFO @ 1940900726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1382) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 112113433870176657319726582347177866503874412823518977591777283290282101399625 84
UVM_INFO @ 19528810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! 1 test run
i2c_target_hrst 55280872626259928606023161065377259551618745531190004813178055592360764231081 85
UVM_INFO @ 10592324067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
i2c_host_stress_all_with_rand_reset 2731805378734089256238102400875198603094523748457260220615316609680788474738 109
UVM_INFO @ 577910712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:714) [scoreboard] controller_mode_rd_obs_fifo item uncompared: 1 test run
i2c_host_mode_toggle 28572851926058129260663159462838597969360659681543496241565504052267368377453 91
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @10141
UVM_ERROR (cip_base_vseq.sv:868) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 1 test run
i2c_same_csr_outstanding 40662349815108979880211892064394808645453274509533111579484051669036567041390 84
UVM_INFO @ 86733092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---