Simulation Results: keymgr_dpe/earlgrey

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 65.08 %
  • code
  • 82.47 %
  • assert
  • 97.67 %
  • func
  • 15.09 %
  • line
  • 97.15 %
  • branch
  • 93.58 %
  • cond
  • 86.46 %
  • toggle
  • 59.49 %
  • FSM
  • 75.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_dpe_smoke 10.070s 617.631us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 1.020s 112.945us 1 1 100.00
csr_rw 1 1 100.00
keymgr_dpe_csr_rw 1.390s 56.054us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 9.790s 1823.605us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 1.810s 45.579us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 1.900s 561.493us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_dpe_csr_rw 1.390s 56.054us 1 1 100.00
keymgr_dpe_csr_aliasing 1.810s 45.579us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
keymgr_dpe_intr_test 1.010s 55.073us 1 1 100.00
alert_test 1 1 100.00
keymgr_dpe_alert_test 1.110s 12.689us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_dpe_tl_errors 2.280s 140.321us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_dpe_tl_errors 2.280s 140.321us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_dpe_csr_hw_reset 1.020s 112.945us 1 1 100.00
keymgr_dpe_csr_rw 1.390s 56.054us 1 1 100.00
keymgr_dpe_csr_aliasing 1.810s 45.579us 1 1 100.00
keymgr_dpe_same_csr_outstanding 1.820s 107.370us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_dpe_csr_hw_reset 1.020s 112.945us 1 1 100.00
keymgr_dpe_csr_rw 1.390s 56.054us 1 1 100.00
keymgr_dpe_csr_aliasing 1.810s 45.579us 1 1 100.00
keymgr_dpe_same_csr_outstanding 1.820s 107.370us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
keymgr_dpe_sec_cm 6.620s 2098.307us 1 1 100.00
keymgr_dpe_tl_intg_err 6.350s 337.934us 1 1 100.00
shadow_reg_update_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.140s 122.886us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.140s 122.886us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.140s 122.886us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.140s 122.886us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 1.040s 27.784us 0 1 0.00
prim_count_check 1 1 100.00
keymgr_dpe_sec_cm 6.620s 2098.307us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_dpe_sec_cm 6.620s 2098.307us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(reg2hw.control_shadowed.slot_src_sel.q < NumInstHwSlot)' 1 test run
keymgr_dpe_shadow_reg_errors 63753004750171536628959439219010354395840470445502841595491075387844749604755 83
UVM_ERROR @ 122885716 ps: (keymgr_dpe.sv:320) [ASSERT FAILED] SrcSelInRange_A
UVM_INFO @ 122885716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(reg2hw.control_shadowed.slot_dst_sel.q < NumInstHwSlot)' 1 test run
keymgr_dpe_shadow_reg_errors_with_csr_rw 10600500390194906281688627589302235966190919303319840760424531075009631224739 83
UVM_ERROR @ 27784377 ps: (keymgr_dpe.sv:321) [ASSERT FAILED] DstSelInRange_A
UVM_INFO @ 27784377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---