Simulation Results: lc_ctrl/volatile_unlock_disabled

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.20 %
  • code
  • 83.21 %
  • assert
  • 94.55 %
  • func
  • 92.83 %
  • line
  • 97.24 %
  • branch
  • 93.61 %
  • cond
  • 79.45 %
  • toggle
  • 84.06 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.350s 51.533us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.320s 34.241us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.030s 14.896us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.550s 48.407us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 149.297us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.180s 23.741us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.030s 14.896us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 149.297us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.570s 215.485us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.670s 787.332us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.980s 33.888us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.050s 52.069us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 10.760s 1103.138us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.910s 1505.471us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 10.760s 1103.138us 1 1 100.00
lc_ctrl_prog_failure 2.050s 52.069us 1 1 100.00
lc_ctrl_errors 6.910s 1505.471us 1 1 100.00
lc_ctrl_security_escalation 5.940s 2339.434us 1 1 100.00
lc_ctrl_jtag_state_failure 27.190s 7330.390us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.730s 432.665us 1 1 100.00
lc_ctrl_jtag_errors 23.720s 2412.498us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 8.440s 653.443us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.820s 817.750us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.730s 432.665us 1 1 100.00
lc_ctrl_jtag_errors 23.720s 2412.498us 1 1 100.00
lc_ctrl_jtag_access 8.630s 2732.935us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.110s 7393.784us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.250s 231.424us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.560s 167.882us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.970s 472.850us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.990s 532.779us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.450s 201.548us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.930s 51.911us 1 1 100.00
lc_ctrl_jtag_alert_test 1.500s 145.447us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.230s 726.747us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.070s 48.896us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 16.590s 2934.992us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.220s 19.186us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.960s 42.428us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.960s 42.428us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.320s 34.241us 1 1 100.00
lc_ctrl_csr_rw 1.030s 14.896us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 149.297us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.190s 17.662us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.320s 34.241us 1 1 100.00
lc_ctrl_csr_rw 1.030s 14.896us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 149.297us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.190s 17.662us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.660s 195.357us 1 1 100.00
lc_ctrl_tl_intg_err 2.570s 514.034us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.570s 514.034us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.670s 787.332us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 10.760s 1103.138us 1 1 100.00
lc_ctrl_sec_cm 6.660s 195.357us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 10.760s 1103.138us 1 1 100.00
lc_ctrl_sec_cm 6.660s 195.357us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 10.760s 1103.138us 1 1 100.00
lc_ctrl_sec_cm 6.660s 195.357us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 10.760s 1103.138us 1 1 100.00
lc_ctrl_sec_cm 6.660s 195.357us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 10.760s 1103.138us 1 1 100.00
lc_ctrl_sec_cm 6.660s 195.357us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 10.760s 1103.138us 1 1 100.00
lc_ctrl_sec_cm 6.660s 195.357us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 10.760s 1103.138us 1 1 100.00
lc_ctrl_sec_cm 6.660s 195.357us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 10.760s 1103.138us 1 1 100.00
lc_ctrl_sec_cm 6.660s 195.357us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.940s 2339.434us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.570s 215.485us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.820s 817.750us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 14.550s 797.516us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 14.550s 797.516us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.840s 255.143us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.220s 2283.724us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.220s 2283.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 40.510s 2772.660us 1 1 100.00