Simulation Results: lc_ctrl/volatile_unlock_enabled

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.47 %
  • code
  • 83.73 %
  • assert
  • 94.13 %
  • func
  • 93.55 %
  • line
  • 97.17 %
  • branch
  • 93.57 %
  • cond
  • 79.35 %
  • toggle
  • 84.99 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.340s 29.131us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.170s 27.090us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.220s 29.593us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.840s 102.969us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 53.755us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.230s 66.537us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.220s 29.593us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 53.755us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.400s 1012.383us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.140s 304.360us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.100s 42.201us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.650s 730.688us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.190s 212.754us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.220s 540.138us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.190s 212.754us 1 1 100.00
lc_ctrl_prog_failure 1.650s 730.688us 1 1 100.00
lc_ctrl_errors 4.220s 540.138us 1 1 100.00
lc_ctrl_security_escalation 6.160s 1148.426us 1 1 100.00
lc_ctrl_jtag_state_failure 36.910s 2930.147us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.390s 855.413us 1 1 100.00
lc_ctrl_jtag_errors 33.350s 3110.490us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.310s 339.986us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.270s 2770.504us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.390s 855.413us 1 1 100.00
lc_ctrl_jtag_errors 33.350s 3110.490us 1 1 100.00
lc_ctrl_jtag_access 3.960s 1267.108us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.520s 940.142us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.540s 187.546us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.410s 180.377us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 13.120s 6988.511us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.070s 378.501us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.120s 93.918us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.820s 127.222us 1 1 100.00
lc_ctrl_jtag_alert_test 1.380s 34.273us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.260s 282.882us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.860s 51.848us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 100.910s 5108.177us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.220s 67.172us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.520s 196.277us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.520s 196.277us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.170s 27.090us 1 1 100.00
lc_ctrl_csr_rw 1.220s 29.593us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 53.755us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.310s 56.591us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.170s 27.090us 1 1 100.00
lc_ctrl_csr_rw 1.220s 29.593us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 53.755us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.310s 56.591us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 8.020s 336.892us 1 1 100.00
lc_ctrl_tl_intg_err 1.470s 175.953us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.470s 175.953us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.140s 304.360us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.190s 212.754us 1 1 100.00
lc_ctrl_sec_cm 8.020s 336.892us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.190s 212.754us 1 1 100.00
lc_ctrl_sec_cm 8.020s 336.892us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.190s 212.754us 1 1 100.00
lc_ctrl_sec_cm 8.020s 336.892us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.190s 212.754us 1 1 100.00
lc_ctrl_sec_cm 8.020s 336.892us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.190s 212.754us 1 1 100.00
lc_ctrl_sec_cm 8.020s 336.892us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.190s 212.754us 1 1 100.00
lc_ctrl_sec_cm 8.020s 336.892us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.190s 212.754us 1 1 100.00
lc_ctrl_sec_cm 8.020s 336.892us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.190s 212.754us 1 1 100.00
lc_ctrl_sec_cm 8.020s 336.892us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.160s 1148.426us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.400s 1012.383us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.270s 2770.504us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.220s 1966.390us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.220s 1966.390us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.260s 306.550us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.700s 233.834us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.700s 233.834us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 11.010s 2439.393us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 86940143782861189677655616351662483195592387175723629188448085886257798525959 213
UVM_INFO @ 2439392854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---