Simulation Results: otbn

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.48 %
  • code
  • 86.16 %
  • assert
  • 89.96 %
  • func
  • 98.31 %
  • block
  • 99.22 %
  • line
  • 99.44 %
  • branch
  • 94.43 %
  • toggle
  • 84.55 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
92.86%
V2S
96.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 16.000s 42.398us 1 1 100.00
otbn_smoke_vectorized 10.000s 59.813us 1 1 100.00
single_binary 1 1 100.00
otbn_single 11.000s 18.321us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 13.631us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 14.131us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 12.000s 156.168us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 5.000s 26.153us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 10.000s 39.111us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 14.131us 1 1 100.00
otbn_csr_aliasing 5.000s 26.153us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 102.000s 11178.458us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 36.000s 1337.706us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 30.000s 189.988us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 89.000s 167.445us 1 1 100.00
back_to_back 0 1 0.00
otbn_multi 15.000s 142.473us 0 1 0.00
stress_all 1 1 100.00
otbn_stress_all 136.000s 5321.350us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 9.000s 15.743us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 8.000s 16.704us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 33.000s 90.626us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 7.000s 88.945us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 5.000s 87.798us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 8.000s 161.272us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 8.000s 161.272us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 5.000s 13.631us 1 1 100.00
otbn_csr_rw 5.000s 14.131us 1 1 100.00
otbn_csr_aliasing 5.000s 26.153us 1 1 100.00
otbn_same_csr_outstanding 6.000s 32.410us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 5.000s 13.631us 1 1 100.00
otbn_csr_rw 5.000s 14.131us 1 1 100.00
otbn_csr_aliasing 5.000s 26.153us 1 1 100.00
otbn_same_csr_outstanding 6.000s 32.410us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 10.000s 53.226us 1 1 100.00
otbn_dmem_err 12.000s 204.688us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 12.000s 55.353us 1 1 100.00
otbn_controller_ispr_rdata_err 13.000s 668.280us 1 1 100.00
otbn_mac_bignum_acc_err 12.000s 53.397us 1 1 100.00
otbn_urnd_err 6.000s 71.630us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 8.000s 10.192us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 10.000s 19.991us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 8.000s 80.701us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 391.000s 6792.676us 1 1 100.00
otbn_tl_intg_err 33.000s 154.527us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 37.000s 378.526us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 391.000s 6792.676us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 391.000s 6792.676us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 16.000s 42.398us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 12.000s 204.688us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 10.000s 53.226us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 33.000s 154.527us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 15.743us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 53.226us 1 1 100.00
otbn_dmem_err 12.000s 204.688us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 16.704us 1 1 100.00
otbn_illegal_mem_acc 8.000s 10.192us 1 1 100.00
otbn_sec_cm 391.000s 6792.676us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 391.000s 6792.676us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 11.000s 18.321us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 53.226us 1 1 100.00
otbn_dmem_err 12.000s 204.688us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 16.704us 1 1 100.00
otbn_illegal_mem_acc 8.000s 10.192us 1 1 100.00
otbn_sec_cm 391.000s 6792.676us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 391.000s 6792.676us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 15.743us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 53.226us 1 1 100.00
otbn_dmem_err 12.000s 204.688us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 16.704us 1 1 100.00
otbn_illegal_mem_acc 8.000s 10.192us 1 1 100.00
otbn_sec_cm 391.000s 6792.676us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 391.000s 6792.676us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 11.000s 18.321us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 10.000s 28.458us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 10.000s 53.746us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 66.000s 264.582us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 66.000s 264.582us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 10.000s 160.699us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 391.000s 6792.676us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 391.000s 6792.676us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 12.000s 119.001us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 391.000s 6792.676us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 391.000s 6792.676us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 14.000s 25.074us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 14.000s 25.074us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 8.000s 21.745us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 18.321us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 18.321us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 11.000s 18.321us 1 1 100.00
sec_cm_write_mem_integrity 0 1 0.00
otbn_multi 15.000s 142.473us 0 1 0.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 11.000s 18.321us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 11.000s 18.321us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 15.000s 77.608us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 11.000s 18.321us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 391.000s 6792.676us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 211.000s 1686.353us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi 22476906403302784382708311122919170441263320725489183524491615044834858641891 154
UVM_INFO @ 142472660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 29403605921969104642360508469846176828574328992524273652067249783469097376744 161
UVM_INFO @ 1686353155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---