Simulation Results: pwrmgr

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 96.02 %
  • code
  • 94.55 %
  • assert
  • 97.13 %
  • func
  • 96.38 %
  • line
  • 98.93 %
  • branch
  • 95.62 %
  • cond
  • 94.20 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
72.73%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.660s 40.833us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.720s 84.885us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.640s 45.659us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.610s 1283.304us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.790s 41.106us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.790s 65.842us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.640s 45.659us 1 1 100.00
pwrmgr_csr_aliasing 0.790s 41.106us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.720s 47.691us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.720s 47.691us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.880s 119.368us 1 1 100.00
pwrmgr_lowpower_invalid 0.710s 44.479us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 2.180s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.720s 183.594us 1 1 100.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 2.180s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.520s 272.618us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.720s 86.225us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.740s 54.976us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 4.260s 2942.224us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.620s 49.997us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.600s 108.290us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.600s 108.290us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.720s 84.885us 1 1 100.00
pwrmgr_csr_rw 0.640s 45.659us 1 1 100.00
pwrmgr_csr_aliasing 0.790s 41.106us 1 1 100.00
pwrmgr_same_csr_outstanding 0.830s 54.559us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.720s 84.885us 1 1 100.00
pwrmgr_csr_rw 0.640s 45.659us 1 1 100.00
pwrmgr_csr_aliasing 0.790s 41.106us 1 1 100.00
pwrmgr_same_csr_outstanding 0.830s 54.559us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 3600.027s 0.000us 0 1 0.00
pwrmgr_sec_cm 3600.027s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 3600.027s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 3600.027s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 3600.027s 0.000us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.940s 1285.276us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 1.520s 272.618us 1 1 100.00
pwrmgr_repeat_wakeup_reset 2.290s 878.474us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.910s 113.461us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.610s 32.546us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 3600.027s 0.000us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 3600.027s 0.000us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 3600.027s 0.000us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.720s 264.439us 1 1 100.00
sec_cm_main_pd_rst_local_esc 0 1 0.00
pwrmgr_glitch 3600.039s 0.000us 0 1 0.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.050s 226.203us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.640s 45.659us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.640s 45.659us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.970s 105.033us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 3600.026s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 4 test runs
pwrmgr_glitch 58697389592466787150952833249134238646934994559433027552478933540941598359222 None
pwrmgr_tl_intg_err 82982725208234454010913993526843465924512216883881017812651414961997336223543 None
pwrmgr_sec_cm 73156952325815827644810729418290984903587604599197361484401623159689671120736 None
pwrmgr_stress_all_with_rand_reset 91887571583517088733358352074796347651664077805251834538934953558147503999110 None
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_reset 68115075186087821979482919790001043381301385551074379375000839222112526143476 136
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---