Simulation Results: rom_ctrl/192kb

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 96.57 %
  • code
  • 95.70 %
  • assert
  • 96.66 %
  • func
  • 97.36 %
  • line
  • 99.21 %
  • branch
  • 99.28 %
  • cond
  • 98.37 %
  • toggle
  • 94.95 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 18.020s 4773.669us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 19.690s 88.319us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 10.420s 66.396us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 10.360s 207.758us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 13.080s 173.416us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 12.320s 93.292us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 10.420s 66.396us 1 1 100.00
rom_ctrl_csr_aliasing 13.080s 173.416us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 10.450s 48.096us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 10.340s 131.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 11.320s 4.767us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 109.640s 3997.523us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 38.960s 4060.789us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 13.840s 54.612us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 20.400s 115.341us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 20.400s 115.341us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 19.690s 88.319us 1 1 100.00
rom_ctrl_csr_rw 10.420s 66.396us 1 1 100.00
rom_ctrl_csr_aliasing 13.080s 173.416us 1 1 100.00
rom_ctrl_same_csr_outstanding 11.340s 83.671us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 19.690s 88.319us 1 1 100.00
rom_ctrl_csr_rw 10.420s 66.396us 1 1 100.00
rom_ctrl_csr_aliasing 13.080s 173.416us 1 1 100.00
rom_ctrl_same_csr_outstanding 11.340s 83.671us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 286.310s 24702.033us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 66.040s 1073.686us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 858.080s 238.762us 1 1 100.00
rom_ctrl_tl_intg_err 192.210s 127.954us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 858.080s 238.762us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 858.080s 238.762us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 286.310s 24702.033us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 286.310s 24702.033us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 286.310s 24702.033us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 286.310s 24702.033us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 286.310s 24702.033us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 858.080s 238.762us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 858.080s 238.762us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 18.020s 4773.669us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 18.020s 4773.669us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 18.020s 4773.669us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 192.210s 127.954us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 286.310s 24702.033us 1 1 100.00
rom_ctrl_kmac_err_chk 38.960s 4060.789us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 286.310s 24702.033us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 286.310s 24702.033us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 286.310s 24702.033us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 66.040s 1073.686us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 858.080s 238.762us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 162.900s 10257.955us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 4004103254206323783591858978502685487825731683324466931927510750542185946697 85
UVM_INFO @ 4766969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---