Simulation Results: rstmgr

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 97.05 %
  • code
  • 99.34 %
  • assert
  • 98.53 %
  • func
  • 93.28 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.96 %
  • toggle
  • 99.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.480s 307.865us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.160s 108.913us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.090s 78.407us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 5.120s 1460.425us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.130s 87.192us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.420s 178.439us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.090s 78.407us 1 1 100.00
rstmgr_csr_aliasing 1.130s 87.192us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.080s 187.317us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.540s 591.164us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.300s 129.076us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.620s 918.448us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.620s 918.448us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.620s 918.448us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.620s 918.448us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 4.840s 1189.286us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.920s 66.704us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.520s 214.906us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.520s 214.906us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.160s 108.913us 1 1 100.00
rstmgr_csr_rw 1.090s 78.407us 1 1 100.00
rstmgr_csr_aliasing 1.130s 87.192us 1 1 100.00
rstmgr_same_csr_outstanding 1.120s 133.533us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.160s 108.913us 1 1 100.00
rstmgr_csr_rw 1.090s 78.407us 1 1 100.00
rstmgr_csr_aliasing 1.130s 87.192us 1 1 100.00
rstmgr_same_csr_outstanding 1.120s 133.533us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 14.360s 8447.481us 1 1 100.00
rstmgr_tl_intg_err 2.960s 974.415us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 14.360s 8447.481us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 14.360s 8447.481us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.960s 974.415us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.910s 113.282us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.620s 1407.208us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.100s 302.285us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 14.360s 8447.481us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.090s 78.407us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.090s 78.407us 1 1 100.00