Simulation Results: rv_timer

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 93.83 %
  • code
  • 94.66 %
  • assert
  • 96.82 %
  • func
  • 90.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.590s 306.868us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.640s 42.200us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.610s 18.214us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.710s 504.491us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.650s 12.992us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.670s 69.735us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.610s 18.214us 1 1 100.00
rv_timer_csr_aliasing 0.650s 12.992us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 0.740s 52.455us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 1.360s 3962.034us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 0.930s 354.024us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 0.930s 354.024us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.260s 2689.839us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.610s 30.844us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.550s 57.544us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.740s 143.289us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.740s 143.289us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.640s 42.200us 1 1 100.00
rv_timer_csr_rw 0.610s 18.214us 1 1 100.00
rv_timer_csr_aliasing 0.650s 12.992us 1 1 100.00
rv_timer_same_csr_outstanding 0.670s 54.391us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.640s 42.200us 1 1 100.00
rv_timer_csr_rw 0.610s 18.214us 1 1 100.00
rv_timer_csr_aliasing 0.650s 12.992us 1 1 100.00
rv_timer_same_csr_outstanding 0.670s 54.391us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.750s 46.769us 1 1 100.00
rv_timer_tl_intg_err 0.840s 418.671us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.840s 418.671us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 5.730s 1560.708us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.620s 198.716us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 17.720s 11141.113us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 3107311814342617820089254450068324965225581988332831992037779899905973786544 84
UVM_INFO @ 1560707859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 104707188694251095846491748449381989803855267719982535554229479883572225895808 81
UVM_INFO @ 198715828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---