Simulation Results: spi_device/1r1w

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 89.25 %
  • code
  • 91.24 %
  • assert
  • 95.40 %
  • func
  • 81.10 %
  • line
  • 98.88 %
  • branch
  • 98.20 %
  • cond
  • 95.64 %
  • toggle
  • 74.14 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 51.460s 19879.051us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.020s 123.629us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.740s 372.696us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 9.390s 1158.469us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 1.310s 58.299us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.910s 553.432us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.740s 372.696us 1 1 100.00
spi_device_csr_aliasing 1.310s 58.299us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.640s 22.572us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.090s 24.054us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.800s 73.132us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.650s 10.393us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.750s 14.539us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.980s 34.555us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.980s 34.555us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 5.020s 2531.694us 1 1 100.00
spi_device_tpm_sts_read 0.680s 27.283us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 19.430s 2991.567us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 1.510s 132.837us 1 1 100.00
spi_device_flash_all 65.920s 19426.985us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.500s 38.863us 1 1 100.00
spi_device_flash_all 65.920s 19426.985us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.500s 38.863us 1 1 100.00
spi_device_flash_all 65.920s 19426.985us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 65.920s 19426.985us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 1.960s 160.522us 1 1 100.00
spi_device_flash_all 65.920s 19426.985us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 1.960s 160.522us 1 1 100.00
spi_device_flash_all 65.920s 19426.985us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 1.960s 160.522us 1 1 100.00
spi_device_flash_all 65.920s 19426.985us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 1.960s 160.522us 1 1 100.00
spi_device_flash_all 65.920s 19426.985us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 1.960s 160.522us 1 1 100.00
spi_device_flash_all 65.920s 19426.985us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 4.080s 973.471us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 4.530s 2788.422us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 4.530s 2788.422us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 4.530s 2788.422us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 9.910s 3794.170us 1 1 100.00
spi_device_read_buffer_direct 2.450s 581.566us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 4.530s 2788.422us 1 1 100.00
spi_device_flash_all 65.920s 19426.985us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 65.920s 19426.985us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 65.920s 19426.985us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.930s 2015.245us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.930s 2015.245us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 24.890s 10267.668us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 51.460s 19879.051us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 176.060s 53259.811us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 243.570s 12014.447us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.790s 33.580us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.840s 58.079us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.470s 2002.752us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.470s 2002.752us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.020s 123.629us 1 1 100.00
spi_device_csr_rw 1.740s 372.696us 1 1 100.00
spi_device_csr_aliasing 1.310s 58.299us 1 1 100.00
spi_device_same_csr_outstanding 3.270s 211.283us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.020s 123.629us 1 1 100.00
spi_device_csr_rw 1.740s 372.696us 1 1 100.00
spi_device_csr_aliasing 1.310s 58.299us 1 1 100.00
spi_device_same_csr_outstanding 3.270s 211.283us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.140s 205.328us 1 1 100.00
spi_device_tl_intg_err 3.870s 108.121us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 3.870s 108.121us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1661) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 27844726970887141827617397077410286432427005425197275842327245421145946390528 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 6085477 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 6085477 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1006])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 95025503212401787548774707441707699444603793768220580681073518292803918846828 76
UVM_ERROR @ 12005600 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x67 [1100111] vs 0x0 [0])
UVM_ERROR @ 12087600 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2e7 [1011100111] vs 0x0 [0])
UVM_ERROR @ 12143600 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x11d [100011101] vs 0x0 [0])
UVM_ERROR @ 12170600 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2c0 [1011000000] vs 0x0 [0])