Simulation Results: spi_host

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.54 %
  • code
  • 91.30 %
  • assert
  • 95.09 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 24.000s 1130.298us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 17.609us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 40.098us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 1106.804us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 8.000s 21.337us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 78.180us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 40.098us 1 1 100.00
spi_host_csr_aliasing 8.000s 21.337us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 17.711us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 17.212us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 8.000s 23.558us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 33.000s 1843.696us 1 1 100.00
spi_host_error_cmd 8.000s 49.054us 1 1 100.00
spi_host_event 16.000s 1015.475us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 9.000s 49.086us 1 1 100.00
speed 1 1 100.00
spi_host_speed 9.000s 49.086us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 9.000s 49.086us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 225.000s 12388.194us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 12.000s 222.211us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 8.000s 61.552us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 9.000s 49.086us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 9.000s 49.086us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 24.000s 1130.298us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 24.000s 1130.298us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 9.000s 246.462us 1 1 100.00
spien 1 1 100.00
spi_host_spien 190.000s 6709.787us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 83.000s 13703.511us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 8.000s 43.999us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 33.000s 1843.696us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 8.000s 17.803us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 49.493us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 1.000s 299.385us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 1.000s 299.385us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 17.609us 1 1 100.00
spi_host_csr_rw 1.000s 40.098us 1 1 100.00
spi_host_csr_aliasing 8.000s 21.337us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 24.942us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 17.609us 1 1 100.00
spi_host_csr_rw 1.000s 40.098us 1 1 100.00
spi_host_csr_aliasing 8.000s 21.337us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 24.942us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 447.803us 1 1 100.00
spi_host_sec_cm 8.000s 117.510us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 447.803us 1 1 100.00