Simulation Results: sram_ctrl/main

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.69 %
  • code
  • 94.24 %
  • assert
  • 97.83 %
  • func
  • 95.00 %
  • block
  • 93.47 %
  • line
  • 94.53 %
  • branch
  • 90.91 %
  • toggle
  • 91.51 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 7.000s 6052.861us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 126.128us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.522us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 2147.229us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 46.091us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 1452.017us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 13.522us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 46.091us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 243.000s 6034.848us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 71.000s 5059.999us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 30.000s 18303.836us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 288.000s 40202.625us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 173.000s 28463.018us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 45.000s 47059.610us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 28.000s 9643.098us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 38.000s 7343.871us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 7.000s 1346.624us 1 1 100.00
sram_ctrl_partial_access_b2b 357.000s 44539.727us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 1147.401us 1 1 100.00
sram_ctrl_throughput_w_partial_write 7.000s 1367.967us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 2773.159us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 18.000s 9584.830us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 1295.676us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 7.000s 6052.861us 1 1 100.00
sram_ctrl_partial_access 7.000s 1346.624us 1 1 100.00
sram_ctrl_access_during_key_req 45.000s 47059.610us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 78.000s 48303.682us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 31.664us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 57.957us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 57.957us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 126.128us 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.522us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 46.091us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 67.102us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 126.128us 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.522us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 46.091us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 67.102us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 22.000s 15417.116us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 230.862us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 648.537us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 230.862us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 648.537us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 18.000s 9584.830us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 18.000s 9584.830us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.522us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 38.000s 7343.871us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 38.000s 7343.871us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 38.000s 7343.871us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 28.000s 9643.098us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3602.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 22.000s 15417.116us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 7.000s 6052.861us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 7.000s 6052.861us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 38.000s 7343.871us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 230.862us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 28.000s 9643.098us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 230.862us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 230.862us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 7.000s 6052.861us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 230.862us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 33.000s 2720.137us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 2913707599173744194262157403158665405264696261017148863255933128558258715627 None
sram_ctrl_mubi_enc_err 2275540624153672439930063560751705944952507728112626683194827143655896554947 None