Simulation Results: sram_ctrl/ret

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.24 %
  • code
  • 81.75 %
  • assert
  • 97.81 %
  • func
  • 91.15 %
  • block
  • 92.19 %
  • line
  • 93.78 %
  • branch
  • 88.23 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 38.362us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 17.903us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 182.572us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 58.883us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 44.035us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 32.757us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 182.572us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 44.035us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 6.000s 118.562us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 7.000s 334.783us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 7.000s 928.996us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 185.000s 29959.087us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 9.000s 996.470us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 10.000s 842.575us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.000s 4667.384us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 9.000s 1998.885us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 261.870us 1 1 100.00
sram_ctrl_partial_access_b2b 236.000s 4830.165us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 169.261us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 37.000us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 42.279us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 399.722us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 79.708us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 2.000s 38.362us 1 1 100.00
sram_ctrl_partial_access 2.000s 261.870us 1 1 100.00
sram_ctrl_access_during_key_req 10.000s 842.575us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 42.000s 6396.968us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 44.882us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 336.443us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 336.443us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 17.903us 1 1 100.00
sram_ctrl_csr_rw 1.000s 182.572us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 44.035us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 74.097us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 17.903us 1 1 100.00
sram_ctrl_csr_rw 1.000s 182.572us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 44.035us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 74.097us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 224.441us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 194.890us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 102.200us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 194.890us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 102.200us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 399.722us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 399.722us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 182.572us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1998.885us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1998.885us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1998.885us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.000s 4667.384us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 224.441us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 38.362us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 38.362us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 9.000s 1998.885us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 194.890us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.000s 4667.384us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 194.890us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 194.890us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 38.362us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 194.890us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 27.000s 1053.931us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 106252773682637744202510212618169797116121637960199895985040559740637363805786 None
sram_ctrl_mubi_enc_err 40996708573196883502657565288869142834529503148486227285281391032299709782670 None