Simulation Results: uart

 
02/09/2026 15:30:33 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 78.56 %
  • code
  • 92.49 %
  • assert
  • 98.27 %
  • func
  • 44.93 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.67 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.820s 844.855us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.600s 61.176us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.630s 32.409us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.780s 318.822us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.840s 67.787us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.730s 102.712us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.630s 32.409us 1 1 100.00
uart_csr_aliasing 0.840s 67.787us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 19.790s 42241.606us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.820s 844.855us 1 1 100.00
uart_tx_rx 19.790s 42241.606us 1 1 100.00
parity_error 2 2 100.00
uart_intr 4.440s 21359.054us 1 1 100.00
uart_rx_parity_err 65.140s 77219.751us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 19.790s 42241.606us 1 1 100.00
uart_intr 4.440s 21359.054us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 27.120s 33522.625us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 29.860s 33246.014us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 31.560s 29765.907us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 4.440s 21359.054us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 4.440s 21359.054us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 4.440s 21359.054us 1 1 100.00
perf 1 1 100.00
uart_perf 40.160s 8447.351us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.230s 3765.794us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.230s 3765.794us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 2.250s 1161.044us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 12.420s 38201.691us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 9.790s 7624.128us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 7.590s 5787.349us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 368.780s 105006.825us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 33.420s 121178.578us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.560s 117.386us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.650s 15.950us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.320s 83.054us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.320s 83.054us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.600s 61.176us 1 1 100.00
uart_csr_rw 0.630s 32.409us 1 1 100.00
uart_csr_aliasing 0.840s 67.787us 1 1 100.00
uart_same_csr_outstanding 0.920s 34.785us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.600s 61.176us 1 1 100.00
uart_csr_rw 0.630s 32.409us 1 1 100.00
uart_csr_aliasing 0.840s 67.787us 1 1 100.00
uart_same_csr_outstanding 0.920s 34.785us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.900s 49.466us 1 1 100.00
uart_tl_intg_err 1.290s 375.512us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.290s 375.512us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 14.980s 1484.026us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:390) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 3627798417546829141609278823265971741066842000567273965424608208726836249622 80
UVM_ERROR @ 31196684 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 160600595 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 160731908 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 160812716 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata