Simulation Results

Simulation Results: adc_ctrl

03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
70.27 %

code
95.65 %

assert
96.76 %

func
18.39 %

line
99.02 %

branch
98.45 %

cond
94.29 %

toggle
100.00 %

FSM
86.49 %

Validation stages

V1		100.00%
V2		89.47%
V2S		50.00%
V3		0.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	adc_ctrl_smoke	11.740s	5861.877us	1	1	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	1.650s	1239.159us	1	1	100.00
csr_rw				1	1	100.00
	adc_ctrl_csr_rw	1.090s	461.949us	1	1	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	46.750s	26623.306us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	1.180s	443.975us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	1.030s	370.843us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	adc_ctrl_csr_rw	1.090s	461.949us	1	1	100.00
	adc_ctrl_csr_aliasing	1.180s	443.975us	1	1	100.00

17/19 passed

89.47 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				1	1	100.00
	adc_ctrl_filters_polled	6.050s	18618.768us	1	1	100.00
filters_polled_fixed				1	1	100.00
	adc_ctrl_filters_polled_fixed	88.020s	35846.424us	1	1	100.00
filters_interrupt				1	1	100.00
	adc_ctrl_filters_interrupt	50.890s	38918.521us	1	1	100.00
filters_interrupt_fixed				1	1	100.00
	adc_ctrl_filters_interrupt_fixed	15.780s	53552.383us	1	1	100.00
filters_wakeup				1	1	100.00
	adc_ctrl_filters_wakeup	29.930s	74360.488us	1	1	100.00
filters_wakeup_fixed				1	1	100.00
	adc_ctrl_filters_wakeup_fixed	27.300s	53153.005us	1	1	100.00
filters_both				1	1	100.00
	adc_ctrl_filters_both	45.450s	27146.088us	1	1	100.00
clock_gating				0	1	0.00
	adc_ctrl_clock_gating	5.830s	12756.857us	0	1	0.00
poweron_counter				1	1	100.00
	adc_ctrl_poweron_counter	12.340s	4642.537us	1	1	100.00
lowpower_counter				1	1	100.00
	adc_ctrl_lowpower_counter	9.460s	29606.822us	1	1	100.00
fsm_reset				1	1	100.00
	adc_ctrl_fsm_reset	54.000s	88759.443us	1	1	100.00
stress_all				0	1	0.00
	adc_ctrl_stress_all	386.440s	201465.411us	0	1	0.00
alert_test				1	1	100.00
	adc_ctrl_alert_test	1.440s	488.288us	1	1	100.00
intr_test				1	1	100.00
	adc_ctrl_intr_test	1.200s	300.449us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	adc_ctrl_tl_errors	1.550s	375.249us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	adc_ctrl_tl_errors	1.550s	375.249us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	adc_ctrl_csr_hw_reset	1.650s	1239.159us	1	1	100.00
	adc_ctrl_csr_rw	1.090s	461.949us	1	1	100.00
	adc_ctrl_csr_aliasing	1.180s	443.975us	1	1	100.00
	adc_ctrl_same_csr_outstanding	3.640s	5425.191us	1	1	100.00
tl_d_partial_access				4	4	100.00
	adc_ctrl_csr_hw_reset	1.650s	1239.159us	1	1	100.00
	adc_ctrl_csr_rw	1.090s	461.949us	1	1	100.00
	adc_ctrl_csr_aliasing	1.180s	443.975us	1	1	100.00
	adc_ctrl_same_csr_outstanding	3.640s	5425.191us	1	1	100.00

V2S

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				1	2	50.00
	adc_ctrl_sec_cm	19.370s	8099.116us	1	1	100.00
	adc_ctrl_tl_intg_err	3.420s	2400.971us	0	1	0.00
sec_cm_bus_integrity				0	1	0.00
	adc_ctrl_tl_intg_err	3.420s	2400.971us	0	1	0.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	adc_ctrl_stress_all_with_rand_reset	12.640s	86685.035us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error				3 test runs
	adc_ctrl_clock_gating	88354454061410019519578885333580269819591169361629296090559968206176938231252	392	UVM_INFO @ 12756856942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	72419534638059999010547328697531455541634332303713267710710580736988310843830	485	UVM_INFO @ 86685034930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	58709147301165710316079465329553155773634545439457103159927026322057625414227	554	UVM_INFO @ 201465411334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [adc_ctrl_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				1 test run
	adc_ctrl_tl_intg_err	38174527062854574472839613718268430869682592770833773530605376649349257907164	445	UVM_INFO @ 2400971471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---