Simulation Results: aes/unmasked

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.47 %
  • code
  • 90.29 %
  • assert
  • 97.73 %
  • func
  • 74.38 %
  • block
  • 90.26 %
  • line
  • 92.62 %
  • branch
  • 81.67 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 61.006us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 182.183us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 66.134us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 97.785us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 3702.076us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 1.000s 129.612us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 86.303us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 97.785us 1 1 100.00
aes_csr_aliasing 1.000s 129.612us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 182.183us 1 1 100.00
aes_config_error 3.000s 63.972us 1 1 100.00
aes_stress 3.000s 208.289us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 182.183us 1 1 100.00
aes_config_error 3.000s 63.972us 1 1 100.00
aes_stress 3.000s 208.289us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 208.289us 1 1 100.00
aes_b2b 3.000s 89.808us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 208.289us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 182.183us 1 1 100.00
aes_config_error 3.000s 63.972us 1 1 100.00
aes_stress 3.000s 208.289us 1 1 100.00
aes_alert_reset 2.000s 71.289us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 70.573us 1 1 100.00
aes_config_error 3.000s 63.972us 1 1 100.00
aes_alert_reset 2.000s 71.289us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 134.144us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 131.533us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 71.289us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 208.289us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 208.289us 1 1 100.00
aes_sideload 2.000s 77.296us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 76.850us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 6.000s 1327.952us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 54.332us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 107.280us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 107.280us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 66.134us 1 1 100.00
aes_csr_rw 2.000s 97.785us 1 1 100.00
aes_csr_aliasing 1.000s 129.612us 1 1 100.00
aes_same_csr_outstanding 2.000s 86.657us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 66.134us 1 1 100.00
aes_csr_rw 2.000s 97.785us 1 1 100.00
aes_csr_aliasing 1.000s 129.612us 1 1 100.00
aes_same_csr_outstanding 2.000s 86.657us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 141.077us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3.000s 127.773us 0 1 0.00
aes_control_fi 2.000s 49.866us 1 1 100.00
aes_cipher_fi 1.000s 54.266us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 83.661us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 83.661us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 83.661us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 83.661us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 136.573us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 2429.983us 1 1 100.00
aes_tl_intg_err 2.000s 322.921us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 322.921us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 71.289us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 83.661us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 83.661us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 182.183us 1 1 100.00
aes_stress 3.000s 208.289us 1 1 100.00
aes_alert_reset 2.000s 71.289us 1 1 100.00
aes_core_fi 3.000s 125.108us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 63.972us 1 1 100.00
aes_stress 3.000s 208.289us 1 1 100.00
aes_core_fi 3.000s 125.108us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 83.661us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 386.069us 1 1 100.00
aes_stress 3.000s 208.289us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 208.289us 1 1 100.00
aes_sideload 2.000s 77.296us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 386.069us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 386.069us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 386.069us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 386.069us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 386.069us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 208.289us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 208.289us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 127.773us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 127.773us 0 1 0.00
aes_control_fi 2.000s 49.866us 1 1 100.00
aes_cipher_fi 1.000s 54.266us 1 1 100.00
aes_ctr_fi 2.000s 52.778us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 127.773us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 127.773us 0 1 0.00
aes_control_fi 2.000s 49.866us 1 1 100.00
aes_cipher_fi 1.000s 54.266us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 54.266us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 127.773us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 127.773us 0 1 0.00
aes_control_fi 2.000s 49.866us 1 1 100.00
aes_ctr_fi 2.000s 52.778us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 127.773us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 127.773us 0 1 0.00
aes_control_fi 2.000s 49.866us 1 1 100.00
aes_cipher_fi 1.000s 54.266us 1 1 100.00
aes_ctr_fi 2.000s 52.778us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 71.289us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 127.773us 0 1 0.00
aes_control_fi 2.000s 49.866us 1 1 100.00
aes_cipher_fi 1.000s 54.266us 1 1 100.00
aes_ctr_fi 2.000s 52.778us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 127.773us 0 1 0.00
aes_control_fi 2.000s 49.866us 1 1 100.00
aes_cipher_fi 1.000s 54.266us 1 1 100.00
aes_ctr_fi 2.000s 52.778us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 127.773us 0 1 0.00
aes_control_fi 2.000s 49.866us 1 1 100.00
aes_ctr_fi 2.000s 52.778us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 127.773us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 127.773us 0 1 0.00
aes_control_fi 2.000s 49.866us 1 1 100.00
aes_cipher_fi 1.000s 54.266us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 50.401us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 63129082681870254725744568249614493214047317439634842109409965824876815389896 3028
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 103723539885964833695438244864430151792124243015789395418396248361790395567098 161
UVM_INFO @ 50401474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---