Simulation Results: alert_handler

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 89.70 %
  • code
  • 90.36 %
  • assert
  • 97.87 %
  • func
  • 80.86 %
  • line
  • 99.66 %
  • branch
  • 98.63 %
  • cond
  • 92.46 %
  • toggle
  • 88.49 %
  • FSM
  • 72.58 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 16.450s 1434.836us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 7.440s 231.700us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.620s 81.635us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 463.020s 10956.143us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 17.880s 1121.516us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 8.820s 160.670us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.620s 81.635us 1 1 100.00
alert_handler_csr_aliasing 17.880s 1121.516us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 11.300s 280.592us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 36.120s 580.889us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 2065.380s 52345.098us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 28.120s 439.044us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 16.450s 1434.836us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 11.740s 147.828us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 29.380s 1333.803us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 238.130s 24302.686us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 2591.710s 141395.156us 1 1 100.00
alert_handler_lpg_stub_clk 2480.340s 108623.214us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 135.000s 5521.777us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 6.260s 458.049us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.790s 268.215us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.770s 18.800us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 13.500s 896.913us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 13.500s 896.913us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 7.440s 231.700us 1 1 100.00
alert_handler_csr_rw 4.620s 81.635us 1 1 100.00
alert_handler_csr_aliasing 17.880s 1121.516us 1 1 100.00
alert_handler_same_csr_outstanding 46.050s 1190.887us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 7.440s 231.700us 1 1 100.00
alert_handler_csr_rw 4.620s 81.635us 1 1 100.00
alert_handler_csr_aliasing 17.880s 1121.516us 1 1 100.00
alert_handler_same_csr_outstanding 46.050s 1190.887us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 152.760s 17740.966us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 152.760s 17740.966us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 152.760s 17740.966us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 152.760s 17740.966us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 896.190s 64885.943us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 17.530s 461.568us 1 1 100.00
alert_handler_tl_intg_err 76.600s 4949.130us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 76.600s 4949.130us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 152.760s 17740.966us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 16.450s 1434.836us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 16.450s 1434.836us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 16.450s 1434.836us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 16.450s 1434.836us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 28.120s 439.044us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 2591.710s 141395.156us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 28.120s 439.044us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2065.380s 52345.098us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2065.380s 52345.098us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 17.530s 461.568us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 17.530s 461.568us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 17.530s 461.568us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 17.530s 461.568us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 17.530s 461.568us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.530s 461.568us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.530s 461.568us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.530s 461.568us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 17.530s 461.568us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 34.100s 611.844us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 78781353706463006852790625743788300011534433333141356721866541342661232492453 206
UVM_INFO @ 458048517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 64185108773345756377516458053435846623429283459234926579278717297784034813014 103
UVM_INFO @ 611843882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---