Simulation Results

Simulation Results: chip

03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
73.72 %

code
75.91 %

assert
96.74 %

func
48.52 %

line
93.78 %

branch
93.30 %

cond
89.08 %

toggle
70.04 %

FSM
33.33 %

Validation stages

V1		100.00%
V2		84.41%
V2S		100.00%
V3		60.00%
unmapped		12.50%

17/17 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				3	3	100.00
	chip_sw_example_rom	121.610s	1868.564us	1	1	100.00
	chip_sw_example_manufacturer	224.020s	2893.879us	1	1	100.00
	chip_sw_example_concurrency	220.510s	3112.008us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	447.710s	10877.076us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	750.150s	11436.283us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	714.010s	12559.102us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	9608.710s	72359.567us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	510.780s	10018.367us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	9608.710s	72359.567us	1	1	100.00
	chip_csr_rw	750.150s	11436.283us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	4.960s	39.566us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	425.550s	3886.043us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	425.550s	3886.043us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	425.550s	3886.043us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	448.310s	3845.337us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	448.310s	3845.337us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	517.040s	4236.192us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	427.050s	3908.593us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	444.840s	4591.958us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	2017.700s	13354.490us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	1220.270s	8033.803us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	358.380s	4065.120us	1	1	100.00

222/263 passed

84.41 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	411.880s	9447.143us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	411.880s	9447.143us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	291.510s	3015.156us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	403.440s	5809.503us	1	1	100.00
chip_sw_sleep_pin_retention				0	1	0.00
	chip_sw_sleep_pin_retention	203.610s	2902.196us	0	1	0.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	951.400s	12144.111us	1	1	100.00
	chip_tap_straps_testunlock0	194.270s	3655.081us	1	1	100.00
	chip_tap_straps_rma	545.020s	8387.470us	1	1	100.00
	chip_tap_straps_prod	156.340s	2744.172us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	549.670s	4641.239us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	549.670s	4641.239us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	678.890s	6569.866us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1044.910s	9390.894us	0	1	0.00
chip_sw_ast_sys_clk_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3959.060s	19083.345us	1	1	100.00
	chip_sw_aes_enc_jitter_en	216.860s	3155.110us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	902.050s	6357.091us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	219.900s	2680.666us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	1269.360s	9703.146us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	309.220s	3493.694us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	423.320s	4401.360us	1	1	100.00
	chip_sw_clkmgr_jitter	217.800s	2450.323us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	292.940s	3199.754us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				1	2	50.00
	chip_sw_sensor_ctrl_alert	624.000s	5813.460us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	188.900s	2348.643us	0	1	0.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	165.980s	2347.227us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				0	1	0.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	188.900s	2348.643us	0	1	0.00
chip_sw_smoketest				16	16	100.00
	chip_sw_aes_smoketest	235.080s	2943.279us	1	1	100.00
	chip_sw_aon_timer_smoketest	273.820s	2719.560us	1	1	100.00
	chip_sw_clkmgr_smoketest	224.200s	3350.918us	1	1	100.00
	chip_sw_csrng_smoketest	250.560s	2807.054us	1	1	100.00
	chip_sw_entropy_src_smoketest	1081.360s	6470.672us	1	1	100.00
	chip_sw_gpio_smoketest	237.200s	2792.374us	1	1	100.00
	chip_sw_hmac_smoketest	231.770s	2898.007us	1	1	100.00
	chip_sw_kmac_smoketest	258.920s	2850.748us	1	1	100.00
	chip_sw_otbn_smoketest	949.550s	6757.176us	1	1	100.00
	chip_sw_pwrmgr_smoketest	300.510s	5427.068us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	326.860s	5246.491us	1	1	100.00
	chip_sw_rv_plic_smoketest	256.210s	2670.602us	1	1	100.00
	chip_sw_rv_timer_smoketest	233.360s	2832.520us	1	1	100.00
	chip_sw_rstmgr_smoketest	187.740s	2325.924us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	204.070s	2961.112us	1	1	100.00
	chip_sw_uart_smoketest	184.930s	2996.561us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	230.720s	3120.088us	1	1	100.00
chip_sw_rom_functests				1	1	100.00
	rom_keymgr_dpe_functest	332.130s	3745.728us	1	1	100.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	20866.240s	127135.358us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3627.320s	15143.612us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	1043.530s	25859.307us	0	1	0.00
chip_sw_power_idle_load				1	1	100.00
	chip_sw_power_idle_load	533.910s	4041.306us	1	1	100.00
chip_sw_power_sleep_load				1	1	100.00
	chip_sw_power_sleep_load	335.300s	9471.183us	1	1	100.00
chip_sw_exit_test_unlocked_bootstrap				0	1	0.00
	chip_sw_exit_test_unlocked_bootstrap	13200.144s	0.000us	0	1	0.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	3209.020s	60000.000us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	3209.020s	60000.000us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	9608.710s	72359.567us	1	1	100.00
	chip_same_csr_outstanding	2465.150s	30530.498us	1	1	100.00
	chip_csr_hw_reset	447.710s	10877.076us	1	1	100.00
	chip_csr_rw	750.150s	11436.283us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	9608.710s	72359.567us	1	1	100.00
	chip_same_csr_outstanding	2465.150s	30530.498us	1	1	100.00
	chip_csr_hw_reset	447.710s	10877.076us	1	1	100.00
	chip_csr_rw	750.150s	11436.283us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	33.800s	1097.332us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	5.490s	48.609us	1	1	100.00
	xbar_smoke_large_delays	60.500s	8782.566us	1	1	100.00
	xbar_smoke_slow_rsp	50.250s	4800.948us	1	1	100.00
	xbar_random_zero_delays	30.550s	476.944us	1	1	100.00
	xbar_random_large_delays	308.420s	45407.610us	1	1	100.00
	xbar_random_slow_rsp	296.950s	29264.221us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	44.360s	1423.506us	1	1	100.00
	xbar_error_and_unmapped_addr	13.330s	333.978us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	12.200s	145.392us	1	1	100.00
	xbar_error_and_unmapped_addr	13.330s	333.978us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	45.550s	882.631us	1	1	100.00
	xbar_access_same_device_slow_rsp	607.890s	55114.372us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	14.110s	175.372us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	102.400s	2123.441us	1	1	100.00
	xbar_stress_all_with_error	63.300s	2520.272us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	144.820s	460.644us	1	1	100.00
	xbar_stress_all_with_reset_error	233.810s	5382.640us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3627.320s	15143.612us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	3500.840s	34727.173us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3784.010s	23026.717us	1	1	100.00
rom_e2e_boot_policy_valid				15	15	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	2871.400s	11208.913us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	3901.660s	16194.400us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	4162.420s	16130.792us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	4057.640s	15919.584us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	3532.940s	15175.881us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	2992.670s	11780.873us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	3709.540s	15654.657us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	3801.220s	15892.738us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	3814.930s	16952.899us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	3783.480s	14919.733us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	4917.150s	17902.661us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	7007.930s	24551.546us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	6921.930s	24343.350us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	6645.170s	24531.052us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	6223.190s	23721.600us	1	1	100.00
rom_e2e_sigverify_always				15	15	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	5502.920s	33442.922us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	6814.240s	30685.213us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	6827.420s	30409.781us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	6832.270s	31541.749us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	6103.950s	21536.988us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	3550.220s	22110.478us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	3752.720s	18850.029us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	3813.130s	20647.375us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	4147.750s	25022.084us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	3257.420s	14671.690us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	2884.440s	11883.083us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	4121.070s	21849.357us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	3797.830s	21622.677us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	3893.770s	26525.793us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	3872.420s	22996.455us	1	1	100.00
rom_e2e_asm_init				5	5	100.00
	rom_e2e_asm_init_test_unlocked0	2768.870s	10762.804us	1	1	100.00
	rom_e2e_asm_init_dev	4029.660s	15306.279us	1	1	100.00
	rom_e2e_asm_init_prod	3913.810s	16028.615us	1	1	100.00
	rom_e2e_asm_init_prod_end	3829.240s	15505.309us	1	1	100.00
	rom_e2e_asm_init_rma	3472.030s	15622.606us	1	1	100.00
rom_e2e_keymgr_dpe_init				3	3	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_meas	7406.570s	29439.334us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_no_meas	7368.170s	29845.324us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas	7805.870s	31079.782us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3974.050s	15787.503us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.163s	0.000us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.163s	0.000us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	190.890s	2310.444us	1	1	100.00
	chip_sw_aes_enc_jitter_en	216.860s	3155.110us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	197.400s	2481.254us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	191.920s	2809.516us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	1557.320s	9801.330us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	246.970s	3062.289us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	503.640s	5392.605us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	458.380s	4590.919us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	561.260s	4789.125us	1	1	100.00
	chip_plic_all_irqs_10	303.120s	3235.712us	1	1	100.00
	chip_plic_all_irqs_20	363.180s	3853.833us	1	1	100.00
chip_sw_alert_handler_entropy				0	1	0.00
	chip_sw_alert_handler_entropy	243.780s	3118.801us	0	1	0.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1376.930s	12183.251us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	260.500s	2833.198us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	227.540s	2628.795us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	262.150s	3130.515us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1430.590s	8459.708us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1019.270s	6115.499us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	927.580s	7945.857us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	11794.100s	255438.952us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	315.050s	3800.213us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	300.510s	5427.068us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	315.050s	3800.213us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	513.770s	6527.015us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	513.770s	6527.015us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	389.220s	6719.613us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	514.470s	4938.805us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	695.300s	6270.417us	1	1	100.00
	chip_sw_aes_idle	191.920s	2809.516us	1	1	100.00
	chip_sw_hmac_enc_idle	264.200s	3313.821us	1	1	100.00
	chip_sw_kmac_idle	263.860s	3290.886us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	471.290s	4908.646us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	306.460s	3886.637us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	383.550s	4163.394us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	408.640s	4986.735us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	836.900s	8876.985us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	522.390s	4088.852us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	460.950s	4302.059us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	481.770s	4164.828us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	485.550s	4365.229us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	470.160s	3908.180us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	464.230s	4440.923us	1	1	100.00
	chip_sw_ast_clk_outputs	678.890s	6569.866us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	1845.320s	27556.767us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	481.770s	4164.828us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	485.550s	4365.229us	1	1	100.00
chip_sw_clkmgr_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3959.060s	19083.345us	1	1	100.00
	chip_sw_aes_enc_jitter_en	216.860s	3155.110us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	902.050s	6357.091us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	219.900s	2680.666us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	1269.360s	9703.146us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	309.220s	3493.694us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	423.320s	4401.360us	1	1	100.00
	chip_sw_clkmgr_jitter	217.800s	2450.323us	1	1	100.00
chip_sw_clkmgr_extended_range				8	8	100.00
	chip_sw_clkmgr_jitter_reduced_freq	168.940s	2798.329us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4362.820s	25476.249us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	189.150s	2825.688us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	223.820s	2666.363us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	1650.850s	12652.610us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	239.560s	3246.127us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	419.590s	5107.809us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	11079.260s	84708.311us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	678.890s	6569.866us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				0	1	0.00
	chip_sw_clkmgr_sleep_frequency	439.890s	4004.162us	0	1	0.00
chip_sw_clkmgr_reset_frequency				0	1	0.00
	chip_sw_clkmgr_reset_frequency	653.560s	11665.629us	0	1	0.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	458.380s	4590.919us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1430.590s	8459.708us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	1127.650s	6968.511us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	362.520s	3676.487us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	813.410s	8523.868us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	192.640s	2340.523us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	6538.850s	32925.381us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	242.860s	2627.929us	1	1	100.00
	chip_sw_edn_entropy_reqs	797.990s	6160.659us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	242.860s	2627.929us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	1127.650s	6968.511us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	228.070s	2982.475us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	275.930s	3151.147us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	219.900s	2680.666us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	264.200s	3313.821us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	1473.570s	8894.761us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	2231.300s	12010.160us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	487.660s	5039.936us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	424.340s	4048.061us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	445.690s	4892.787us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	366.900s	3686.069us	1	1	100.00
chip_sw_keymgr_dpe_key_derivation				2	2	100.00
	chip_sw_keymgr_dpe_key_derivation	1929.050s	12289.949us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	1269.360s	9703.146us	1	1	100.00
chip_sw_keymgr_dpe_sideload_kmac				1	1	100.00
	chip_sw_keymgr_dpe_sideload_kmac	1793.560s	10396.174us	1	1	100.00
chip_sw_keymgr_dpe_sideload_aes				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	1557.320s	9801.330us	1	1	100.00
chip_sw_keymgr_dpe_sideload_otbn				0	1	0.00
	chip_sw_keymgr_dpe_sideload_otbn	3600.154s	0.000us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	256.270s	2808.653us	1	1	100.00
	chip_sw_kmac_mode_kmac	222.530s	2548.279us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	309.220s	3493.694us	1	1	100.00
chip_sw_kmac_app_keymgr_dpe				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1929.050s	12289.949us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	939.390s	15861.832us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	365.790s	7207.107us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	853.600s	5537.970us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	263.860s	3290.886us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	503.640s	5392.605us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	951.400s	12144.111us	1	1	100.00
	chip_tap_straps_rma	545.020s	8387.470us	1	1	100.00
	chip_tap_straps_prod	156.340s	2744.172us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	169.530s	2725.137us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	939.390s	15861.832us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	939.390s	15861.832us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	939.390s	15861.832us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_prod	1376.780s	8643.416us	1	1	100.00
chip_sw_lc_ctrl_broadcast				18	21	85.71
	chip_sw_rram_rma_unlocked	557.810s	10010.360us	0	1	0.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	297.360s	3118.358us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	659.560s	6139.654us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	626.100s	5805.390us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	687.040s	5993.517us	0	1	0.00
	chip_sw_lc_ctrl_transition	939.390s	15861.832us	1	1	100.00
	chip_sw_rram_ctrl_lc_rw_en	473.890s	4900.908us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1929.050s	12289.949us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	870.270s	18085.024us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	678.510s	7681.890us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	1845.320s	27556.767us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	522.390s	4088.852us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	460.950s	4302.059us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	481.770s	4164.828us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	485.550s	4365.229us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	470.160s	3908.180us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	464.230s	4440.923us	1	1	100.00
	chip_tap_straps_dev	951.400s	12144.111us	1	1	100.00
	chip_tap_straps_rma	545.020s	8387.470us	1	1	100.00
	chip_tap_straps_prod	156.340s	2744.172us	1	1	100.00
	chip_rv_dm_lc_disabled	126.060s	4394.967us	0	1	0.00
chip_lc_scrap				2	4	50.00
	chip_sw_lc_ctrl_rma_to_scrap	433.510s	6056.130us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	538.120s	10088.009us	0	1	0.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	510.040s	8613.712us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	614.480s	11632.592us	0	1	0.00
chip_lc_test_locked				0	2	0.00
	chip_sw_lc_walkthrough_testunlocks	3246.310s	60000.000us	0	1	0.00
	chip_rv_dm_lc_disabled	126.060s	4394.967us	0	1	0.00
chip_sw_lc_walkthrough				1	5	20.00
	chip_sw_lc_walkthrough_dev	1741.850s	19816.136us	0	1	0.00
	chip_sw_lc_walkthrough_prod	1724.870s	21137.375us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	1538.080s	16043.834us	1	1	100.00
	chip_sw_lc_walkthrough_rma	1194.010s	15820.302us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	3246.310s	60000.000us	0	1	0.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	1097.150s	25826.837us	0	1	0.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	220.260s	4132.489us	1	1	100.00
	rom_volatile_raw_unlock	273.980s	6017.677us	1	1	100.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3916.460s	17484.450us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3959.060s	19083.345us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	695.300s	6270.417us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	695.300s	6270.417us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	695.300s	6270.417us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	352.220s	3586.283us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	939.390s	15861.832us	1	1	100.00
chip_sw_otp_ctrl_keys				3	4	75.00
	chip_sw_otbn_mem_scramble	352.220s	3586.283us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1929.050s	12289.949us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	491.010s	4779.121us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	3600.154s	0.000us	0	1	0.00
chip_sw_otp_ctrl_entropy				3	4	75.00
	chip_sw_otbn_mem_scramble	352.220s	3586.283us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1929.050s	12289.949us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	491.010s	4779.121us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	3600.154s	0.000us	0	1	0.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	939.390s	15861.832us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	415.680s	5206.424us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	169.530s	2725.137us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				4	5	80.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	297.360s	3118.358us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	659.560s	6139.654us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	626.100s	5805.390us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	687.040s	5993.517us	0	1	0.00
	chip_sw_lc_ctrl_transition	939.390s	15861.832us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	1020.810s	6644.644us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	338.600s	6623.763us	1	1	100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	227.150s	2353.044us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	146.980s	2363.634us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_deep_sleep_por_reset	432.350s	7528.186us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_por_reset	307.310s	4112.239us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	917.250s	22427.192us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				2	2	100.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	952.410s	14687.369us	1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	513.770s	6527.015us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	202.110s	2473.978us	0	1	0.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	382.670s	3536.089us	1	1	100.00
chip_sw_pwrmgr_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	338.600s	6623.763us	1	1	100.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	272.060s	3373.233us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	989.990s	12866.566us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	335.570s	5132.600us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	172.720s	2727.957us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	446.740s	7226.670us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	747.730s	6665.220us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	948.080s	9211.021us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1939.360s	23219.594us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	216.420s	3297.436us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	458.380s	4590.919us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	870.270s	18085.024us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	870.270s	18085.024us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	948.080s	9211.021us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	446.740s	7226.670us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	382.670s	3536.089us	1	1	100.00
	chip_sw_pwrmgr_smoketest	300.510s	5427.068us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	305.520s	4562.701us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	369.460s	4541.751us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	411.660s	4100.586us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1376.930s	12183.251us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	233.430s	2661.298us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	458.380s	4590.919us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1019.270s	6115.499us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	562.380s	4565.270us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	639.860s	4410.827us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	229.200s	3189.949us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				0	1	0.00
	chip_sw_rv_core_ibex_icache_invalidate	3600.154s	0.000us	0	1	0.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	369.460s	4541.751us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	369.460s	4541.751us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	210.310s	2621.899us	1	1	100.00
chip_jtag_csr_rw				0	1	0.00
	chip_jtag_csr_rw	95.050s	2053.744us	0	1	0.00
chip_jtag_mem_access				0	1	0.00
	chip_jtag_mem_access	103.240s	2764.697us	0	1	0.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	305.520s	4562.701us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	248.380s	2555.602us	0	1	0.00
chip_rv_dm_access_after_wakeup				0	1	0.00
	chip_sw_rv_dm_access_after_wakeup	239.680s	2397.389us	0	1	0.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	545.020s	8387.470us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	126.060s	4394.967us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	561.260s	4789.125us	1	1	100.00
	chip_plic_all_irqs_10	303.120s	3235.712us	1	1	100.00
	chip_plic_all_irqs_20	363.180s	3853.833us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	184.000s	2057.068us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	264.120s	3099.834us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3627.320s	15143.612us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	358.060s	3804.608us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	199.010s	2834.604us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	300.960s	3593.912us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	224.740s	2706.494us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	491.010s	4779.121us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	423.320s	4401.360us	1	1	100.00
chip_sw_sleep_sram_ret_contents				0	2	0.00
	chip_sw_sleep_sram_ret_contents_no_scramble	204.620s	2979.053us	0	1	0.00
	chip_sw_sleep_sram_ret_contents_scramble	260.340s	2832.404us	0	1	0.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	678.510s	7681.890us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	458.380s	4590.919us	1	1	100.00
	chip_sw_data_integrity_escalation	549.670s	4641.239us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	747.730s	6665.220us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1044.730s	22682.172us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	212.770s	2649.318us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	289.950s	3619.905us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	403.940s	4143.952us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1044.730s	22682.172us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1044.730s	22682.172us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	3028.980s	20860.585us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	3028.980s	20860.585us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	417.000s	5701.340us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.163s	0.000us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	216.360s	2260.699us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	239.270s	2824.628us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	338.910s	3883.531us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	370.840s	4078.377us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	946.750s	8190.014us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	6416.640s	31329.784us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	2367.030s	12264.733us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	219.320s	2237.219us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	216.440s	2744.121us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	153.650s	2535.522us	1	1	100.00

15/25 passed

60.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	13340.020s	72203.090us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1397.840s	6528.229us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	83.240s	2241.350us	0	1	0.00
	rom_e2e_jtag_debug_dev	86.000s	2087.932us	0	1	0.00
	rom_e2e_jtag_debug_rma	98.790s	2253.733us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	94.170s	1733.178us	0	1	0.00
	rom_e2e_jtag_inject_dev	113.380s	2061.164us	0	1	0.00
	rom_e2e_jtag_inject_rma	116.840s	2694.477us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	274.368s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	332.780s	3661.984us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	392.600s	2940.669us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	489.550s	3195.500us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1896.370s	11410.369us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	341.510s	2490.309us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	226.210s	2817.499us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	343.330s	5595.164us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	377.870s	4082.898us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	948.080s	9211.021us	1	1	100.00
chip_sw_rom_ctrl_digests				1	1	100.00
	chip_sw_kmac_app_rom	365.790s	7207.107us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	83.240s	2241.350us	0	1	0.00
	rom_e2e_jtag_debug_dev	86.000s	2087.932us	0	1	0.00
	rom_e2e_jtag_debug_rma	98.790s	2253.733us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	366.820s	4431.778us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	458.380s	4590.919us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	6241.180s	37967.558us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	6241.180s	37967.558us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				0	1	0.00
	chip_sw_spi_device_pinmux_sleep_retention	223.410s	3103.704us	0	1	0.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	448.310s	3845.337us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3716.880s	18519.969us	1	1	100.00

unmapped

1/8 passed

12.50 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	8	12.50
	chip_sw_rstmgr_rst_cnsty_escalation	54.150s	10.360us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	101.460s	2493.098us	0	1	0.00
	chip_sw_otp_ctrl_descrambling	212.860s	2920.564us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	202.320s	3001.732us	0	1	0.00
	chip_sw_pwrmgr_sleep_wake_5_bug	10.586s	0.000us	0	1	0.00
	ate_bootstrap_flash_erase	867.540s	10010.400us	0	1	0.00
	ate_bootstrap_one_frame	10800.143s	0.000us	0	1	0.00
	ate_bootstrap_disjoint	10800.147s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error				12 test runs
	chip_sw_sleep_pin_retention	62342662155426433327193131507915098334958157834931529014539546839539696716876	379	UVM_INFO @ 2902.196178 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_spi_device_pinmux_sleep_retention	56620085173988906099382981071647707868615381145540415763199274784651036517881	374	UVM_INFO @ 3103.704314 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	10454747214454317119634519390733944955678973504507915566551437842898869817457	392	UVM_INFO @ 7226.670366 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	71472116700446465062505510397150862692883100561943148805691672194392311042581	377	UVM_INFO @ 2473.977936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_por_reset	78111954119732646794375479453572577276568958676963140548750703989313074862787	388	UVM_INFO @ 4112.239208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_no_scramble	36816605223560588408635559476507961300609373320088318511935956817233496734523	377	UVM_INFO @ 2979.053416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_scramble	50415589505706169024719304393161500343187816784260807951869974390916261368379	381	UVM_INFO @ 2832.404204 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	107772743925575016958888516471793132799757867330993994847002307579000128557841	372	UVM_INFO @ 2348.643076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_clkmgr_sleep_frequency	37314593672012907287822810331625812786975571556435287767535603467648693339466	407	UVM_INFO @ 4004.161560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	63118333678224692070562136555852646531853110620902156989831865431965723722601	374	UVM_INFO @ 2363.634164 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_lowpower_cancel	32171385450926546961778007461196593553988518691000338868775186343878503958165	372	UVM_INFO @ 3001.731880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_wake_ups	101688974879768798055778405223716237329039880177929685913888593065525059898595	373	UVM_INFO @ 2353.043972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				6 test runs
	chip_sw_exit_test_unlocked_bootstrap	84112132165210893054590865412553841666015695889094056063325816665372828094400	None
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	59175073826813276122007615788398713830665923919517997486575906557209774879723	None
	chip_sw_keymgr_dpe_sideload_otbn	81419401776590825015486239624851575760173391910664200310855450592646819029543	None
	chip_sw_rv_core_ibex_icache_invalidate	91564303979292529516389021433355298343318142044880713639600806662235505602990	None
	ate_bootstrap_one_frame	37897013858057240930761257238514497656253957405227891292749511868453736360996	None
	ate_bootstrap_disjoint	15423279631591807967443197714066968943327112316159236082441893515728525066519	None
Error-[NOA] Null object access				5 test runs
	chip_sw_otp_ctrl_rot_auth_config	59749149705329237892289227066543120228080946338370885072632201434292051755134	383	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	43629338729128359664195519352600532590404315395495483411009350160680859943740	403	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	72322097260229135297898934971177865310848601752223831943497995462581666686158	381	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	60084500946230668881510705910211537282743227626425051274965267020333795286005	379	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	56285410846234399591797790047713421427923047977172035307107132452647786913464	381	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	8171775108349644445180218008778331847399813833364712439499805138846867140704	433	UVM_INFO @ 19816.136182 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	38758570109473826274364157930930490355987774140934572708102288322347264766457	433	UVM_INFO @ 21137.375093 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	56677876101930490396211056482566551067680846620996752368307070431296196340681	405	UVM_INFO @ 15820.301902 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:604) [debugger] Check failed pc == exp_addr (* [] vs [*])				3 test runs
	rom_e2e_jtag_debug_test_unlocked0	100629515652910758791102159023744208637424826213165775274566822468088940914337	359	UVM_INFO @ 2241.350000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_dev	66912665850463676088556928173375223815639734227451337931493747692783012113866	359	UVM_INFO @ 2087.932500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_rma	17500766801892511767025483156682682757149679713721996767351394667552389672035	359	UVM_INFO @ 2253.732500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl				2 test runs
	chip_sw_lc_ctrl_raw_to_scrap	43708540244455713342762294739984192509857570571031317885157636373136548140209	375	UVM_INFO @ 10088.008982 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_ctrl_rand_to_scrap	68027777993210747871087619150593712342361071846022417495539335346994204575797	375	UVM_INFO @ 11632.592322 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue				2 test runs
	chip_sw_lc_walkthrough_testunlocks	83229608810203305899316089544300196020483498969879054956322060935199969357484	491	UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_tl_errors	25057030427534957533269064156139101484106712393013558241785538295806508963378	283	UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				2 test runs
	chip_sw_pwrmgr_sleep_power_glitch_reset	108019040969594489791139577942502349724644753279789124700768210575935507783074	377	UVM_ERROR @ 2727.957080 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 2727.957080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	102085697166634795158388358370695323373245934332525870351963253495508974432957	417	UVM_ERROR @ 12866.565720 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 12866.565720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error				2 test runs
	chip_sw_alert_handler_lpg_sleep_mode_pings	31020470815405083739935405595626563268423899126954453431824499968082847418163	373	UVM_INFO @ 3130.514500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_alert_handler_entropy	85731322057100760193457401442214543045178928933421576534489379901320775059227	494	UVM_INFO @ 3118.801416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_riscv_driver.sv:208) driver [driver] Could not activate RV_DM after * attempts!				2 test runs
	chip_jtag_csr_rw	101661544323156013187477222577666431379956372446466201792178886175536418123816	5365	UVM_INFO @ 2053.744255 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_jtag_mem_access	89167967912039240016790513976455969411919021799175770449279736760158357722199	5365	UVM_INFO @ 2764.696857 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				2 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	61747864964228422598888240412972986938430167733239820086500932130454692917094	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	66135692204572552301629229896524827439656884353587924644545224424443874513224	None	Another command (pid=409717) is running. Waiting for it to complete on the server (server_pid=196481)... Another command (pid=884408) is running. Waiting for it to complete on the server (server_pid=196481)... Another command (pid=884875) is running. Waiting for it to complete on the server (server_pid=196481)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	110139056977047398571475935303001244159271760651277912915890620711091323653681	365	UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch				1 test run
	chip_sw_spi_device_pass_through_collision	347197406781429124869852016044970587653177494549809224496917389293637411822	393	host_rsp: ------------------------------------------------------------------------- Name Type Size Value -------------------------------------------------------------------------
UVM_FATAL @ * us: (chip_sw_rram_rma_unlocked_vseq.sv:162) [chip_sw_rram_rma_unlocked_vseq] wait timeout occurred!				1 test run
	chip_sw_rram_rma_unlocked	95808247069082297097975684358510053366906108644667347521681988835148100283951	337	UVM_INFO @ 10010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	21412361074301904071662655525312616144575475240455083643057494121024540233472	404	UVM_INFO @ 5993.516898 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(buf_intg_err == '0)'				1 test run
	chip_sw_otp_ctrl_escalation	20111595901442599478941165214449647175503449506025486141970388137770959896557	380	UVM_ERROR @ 2817.498952 us: (rram_phy_rd.sv:697) [ASSERT FAILED] IntgError UVM_INFO @ 2817.498952 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] max attempt reached to get lc status LcTokenError!				1 test run
	chip_sw_lc_ctrl_volatile_raw_unlock	68156940749997930925978016119894080559170579917953004959880018650639837710728	372	UVM_INFO @ 25826.837151 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				1 test run
	chip_sw_pwrmgr_deep_sleep_por_reset	4256877790963468221470073167780273632360036001422530130377603057210823288367	389	UVM_ERROR @ 7528.186000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7528.186000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:310)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	24161931405819536403072148717098677046160344891612212368142675395054266764860	371	UVM_INFO @ 3062.288600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	81862120338434085846266443798420472184952026777151040017343208565106826911920	373	UVM_INFO @ 2628.795416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_hmac_multistream	12124985719979304958416795856729085788579730594829999921988707914337988970445	417	UVM_INFO @ 12010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state.				1 test run
	chip_sw_clkmgr_reset_frequency	108224424939054604620787952642324928023211363275524803609875458310073686332274	400	UVM_INFO @ 11665.629217 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	110444812471006534912468103915683156001121378685021301431537279349029347685545	407	UVM_INFO @ 3661.983951 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: jtag_dmi_ral.progbuf_ reset value: * straight after write.				1 test run
	chip_sw_rv_dm_access_after_wakeup	64200892088088139578166945417414440231716550002119874466333878965381019070456	385	UVM_INFO @ 2397.388502 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				1 test run
	chip_rv_dm_lc_disabled	22216708955853872520772973264978939614965008813415974348848911803043870698133	306	UVM_INFO @ 4394.967255 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	103025287769262385937388478658374870718186692940922202104329537524228608410008	391	UVM_INFO @ 9390.893814 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	65457869339013366866629653552058204163846169641975073944861276758326510714751	339	UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] max attempt reached to get lc status LcExtClockSwitched!				1 test run
	rom_raw_unlock	110531363255229602436450688663602274582220354340455865518481968364589562019533	374	UVM_INFO @ 25859.306758 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---