Simulation Results: clkmgr

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 92.98 %
  • code
  • 98.15 %
  • assert
  • 95.20 %
  • func
  • 85.59 %
  • line
  • 98.98 %
  • branch
  • 98.59 %
  • cond
  • 93.98 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.280s 25.443us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.340s 92.712us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.150s 16.125us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 8.560s 1475.921us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.350s 35.117us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.240s 53.257us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.150s 16.125us 1 1 100.00
clkmgr_csr_aliasing 1.350s 35.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.060s 18.842us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.780s 147.807us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.210s 23.820us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.000s 20.249us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.280s 25.443us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 13.630s 2372.468us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 1.850s 263.364us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 13.630s 2372.468us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 25.290s 4182.392us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.250s 56.591us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 3.160s 97.055us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 3.160s 97.055us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 1.340s 92.712us 1 1 100.00
clkmgr_csr_rw 1.150s 16.125us 1 1 100.00
clkmgr_csr_aliasing 1.350s 35.117us 1 1 100.00
clkmgr_same_csr_outstanding 1.820s 119.117us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 1.340s 92.712us 1 1 100.00
clkmgr_csr_rw 1.150s 16.125us 1 1 100.00
clkmgr_csr_aliasing 1.350s 35.117us 1 1 100.00
clkmgr_same_csr_outstanding 1.820s 119.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.860s 3.131us 0 1 0.00
clkmgr_tl_intg_err 3.690s 139.566us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.250s 254.230us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.250s 254.230us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.250s 254.230us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.250s 254.230us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.140s 77.978us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 3.690s 139.566us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 13.630s 2372.468us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 1.850s 263.364us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.250s 254.230us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.090s 20.343us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.170s 31.097us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.000s 21.426us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.170s 20.088us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.270s 27.611us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.150s 16.125us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.860s 3.131us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.150s 16.125us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.150s 16.125us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.860s 3.131us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 5.690s 1493.461us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 66.360s 4626.508us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 47121056188083369656890548786126842091611840743038522036179594482758794886517 84
UVM_INFO @ 3131110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---