Simulation Results: edn/edn0

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 84.04 %
  • code
  • 77.90 %
  • assert
  • 95.44 %
  • func
  • 78.77 %
  • line
  • 96.63 %
  • branch
  • 88.42 %
  • cond
  • 84.91 %
  • toggle
  • 73.29 %
  • FSM
  • 46.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.290s 24.611us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.110s 52.519us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.240s 75.092us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.660s 308.048us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.160s 49.599us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.530s 55.525us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.240s 75.092us 1 1 100.00
edn_csr_aliasing 1.160s 49.599us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 3.350s 76.673us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 3.350s 76.673us 1 1 100.00
genbits 1 1 100.00
edn_genbits 3.350s 76.673us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.460s 22.428us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.570s 226.854us 1 1 100.00
errs 1 1 100.00
edn_err 1.560s 162.396us 1 1 100.00
disable 2 2 100.00
edn_disable 1.140s 52.475us 1 1 100.00
edn_disable_auto_req_mode 1.680s 66.461us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.810s 294.070us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.180s 23.718us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.120s 90.637us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.820s 52.573us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.820s 52.573us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.110s 52.519us 1 1 100.00
edn_csr_rw 1.240s 75.092us 1 1 100.00
edn_csr_aliasing 1.160s 49.599us 1 1 100.00
edn_same_csr_outstanding 1.570s 94.950us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.110s 52.519us 1 1 100.00
edn_csr_rw 1.240s 75.092us 1 1 100.00
edn_csr_aliasing 1.160s 49.599us 1 1 100.00
edn_same_csr_outstanding 1.570s 94.950us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.710s 323.210us 1 1 100.00
edn_tl_intg_err 3.020s 689.501us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.360s 30.423us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.570s 226.854us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.710s 323.210us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.710s 323.210us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.710s 323.210us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.710s 323.210us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.570s 226.854us 1 1 100.00
edn_sec_cm 5.710s 323.210us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.570s 226.854us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.020s 689.501us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 64.180s 10320.473us 1 1 100.00