Simulation Results: edn/edn1

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 86.95 %
  • code
  • 81.95 %
  • assert
  • 98.44 %
  • func
  • 80.46 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 88.00 %
  • toggle
  • 85.94 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.170s 49.503us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.320s 24.121us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.950s 32.478us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.000s 418.894us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.300s 17.428us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.330s 43.523us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.950s 32.478us 1 1 100.00
edn_csr_aliasing 1.300s 17.428us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.710s 78.387us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.710s 78.387us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.710s 78.387us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.200s 41.135us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.610s 75.115us 1 1 100.00
errs 1 1 100.00
edn_err 1.140s 22.496us 1 1 100.00
disable 2 2 100.00
edn_disable 1.190s 52.680us 1 1 100.00
edn_disable_auto_req_mode 1.530s 112.422us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.210s 487.934us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.140s 14.602us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.210s 16.971us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.650s 35.028us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.650s 35.028us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.320s 24.121us 1 1 100.00
edn_csr_rw 0.950s 32.478us 1 1 100.00
edn_csr_aliasing 1.300s 17.428us 1 1 100.00
edn_same_csr_outstanding 1.680s 36.811us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.320s 24.121us 1 1 100.00
edn_csr_rw 0.950s 32.478us 1 1 100.00
edn_csr_aliasing 1.300s 17.428us 1 1 100.00
edn_same_csr_outstanding 1.680s 36.811us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.850s 431.690us 1 1 100.00
edn_tl_intg_err 2.060s 62.716us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.180s 31.946us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.610s 75.115us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.850s 431.690us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.850s 431.690us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.850s 431.690us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.850s 431.690us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.610s 75.115us 1 1 100.00
edn_sec_cm 3.850s 431.690us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.610s 75.115us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.060s 62.716us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 26.380s 1428.597us 1 1 100.00