Simulation Results: entropy_src/rng_4bits

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 71.81 %
  • code
  • 84.62 %
  • assert
  • 83.91 %
  • func
  • 46.91 %
  • block
  • 93.56 %
  • line
  • 96.49 %
  • branch
  • 84.61 %
  • toggle
  • 76.12 %
  • FSM
  • 81.25 %
Validation stages
V1
100.00%
V2
93.75%
V2S
85.71%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 94.040us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 1.000s 32.918us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 84.986us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 7.000s 827.270us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 2.000s 73.201us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 44.537us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 84.986us 1 1 100.00
entropy_src_csr_aliasing 2.000s 73.201us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 2 3 66.67
entropy_src_smoke 2.000s 94.040us 1 1 100.00
entropy_src_rng 197.000s 10453.870us 0 1 0.00
entropy_src_fw_ov 269.000s 14030.278us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 269.000s 14030.278us 1 1 100.00
rng_mode 0 1 0.00
entropy_src_rng 197.000s 10453.870us 0 1 0.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 54.000s 14715.557us 1 1 100.00
health_checks 0 1 0.00
entropy_src_rng 197.000s 10453.870us 0 1 0.00
conditioning 0 1 0.00
entropy_src_rng 197.000s 10453.870us 0 1 0.00
interrupts 1 2 50.00
entropy_src_rng 197.000s 10453.870us 0 1 0.00
entropy_src_intr 17.000s 850.872us 1 1 100.00
alerts 1 2 50.00
entropy_src_rng 197.000s 10453.870us 0 1 0.00
entropy_src_functional_alerts 6.000s 726.734us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 134.000s 13255.103us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 47.744us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 4.000s 42.153us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 38.129us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 28.083us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 84.747us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 84.747us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 32.918us 1 1 100.00
entropy_src_csr_rw 2.000s 84.986us 1 1 100.00
entropy_src_csr_aliasing 2.000s 73.201us 1 1 100.00
entropy_src_same_csr_outstanding 1.000s 66.676us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 32.918us 1 1 100.00
entropy_src_csr_rw 2.000s 84.986us 1 1 100.00
entropy_src_csr_aliasing 2.000s 73.201us 1 1 100.00
entropy_src_same_csr_outstanding 1.000s 66.676us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 326.130us 1 1 100.00
entropy_src_tl_intg_err 4.000s 716.691us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
entropy_src_rng 197.000s 10453.870us 0 1 0.00
entropy_src_cfg_regwen 2.000s 92.876us 1 1 100.00
sec_cm_config_mubi 0 1 0.00
entropy_src_rng 197.000s 10453.870us 0 1 0.00
sec_cm_config_redun 0 1 0.00
entropy_src_rng 197.000s 10453.870us 0 1 0.00
sec_cm_intersig_mubi 1 2 50.00
entropy_src_rng 197.000s 10453.870us 0 1 0.00
entropy_src_fw_ov 269.000s 14030.278us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 47.744us 1 1 100.00
entropy_src_sec_cm 3.000s 326.130us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 47.744us 1 1 100.00
entropy_src_sec_cm 3.000s 326.130us 1 1 100.00
sec_cm_rng_bkgn_chk 0 1 0.00
entropy_src_rng 197.000s 10453.870us 0 1 0.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 47.744us 1 1 100.00
entropy_src_sec_cm 3.000s 326.130us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 47.744us 1 1 100.00
entropy_src_sec_cm 3.000s 326.130us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 47.744us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 6.000s 726.734us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 716.691us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 94.000s 14201.242us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 11.000s 8670.551us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert recov_alert has unexpected timeout error 1 test run
entropy_src_rng 3866172460912354653933657673624897211422313092324985861347949650021856851246 1513
UVM_INFO @ 10453869962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 10422324195983564577262812540150447784762130297870153279984477944877899950653 119
UVM_INFO @ 8670550957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---