Simulation Results: hmac

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 75.78 %
  • code
  • 86.91 %
  • assert
  • 97.60 %
  • func
  • 42.83 %
  • line
  • 99.64 %
  • branch
  • 98.86 %
  • cond
  • 95.74 %
  • toggle
  • 46.17 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 17.270s 601.286us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.990s 22.348us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.070s 113.049us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 5.580s 165.118us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 1.960s 144.248us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 499.400s 96138.250us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.070s 113.049us 1 1 100.00
hmac_csr_aliasing 1.960s 144.248us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 30.920s 3264.889us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 70.300s 7998.845us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 10.600s 263.788us 1 1 100.00
hmac_test_sha384_vectors 398.390s 16789.628us 1 1 100.00
hmac_test_sha512_vectors 30.720s 897.923us 1 1 100.00
hmac_test_hmac256_vectors 9.490s 298.132us 1 1 100.00
hmac_test_hmac384_vectors 10.890s 1197.956us 1 1 100.00
hmac_test_hmac512_vectors 16.180s 464.513us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 23.530s 10712.587us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 885.100s 9067.862us 1 1 100.00
error 1 1 100.00
hmac_error 128.380s 12753.133us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 50.870s 3043.588us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 17.270s 601.286us 1 1 100.00
hmac_long_msg 30.920s 3264.889us 1 1 100.00
hmac_back_pressure 70.300s 7998.845us 1 1 100.00
hmac_datapath_stress 885.100s 9067.862us 1 1 100.00
hmac_burst_wr 23.530s 10712.587us 1 1 100.00
hmac_stress_all 1426.750s 170372.507us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 17.270s 601.286us 1 1 100.00
hmac_long_msg 30.920s 3264.889us 1 1 100.00
hmac_back_pressure 70.300s 7998.845us 1 1 100.00
hmac_datapath_stress 885.100s 9067.862us 1 1 100.00
hmac_wipe_secret 50.870s 3043.588us 1 1 100.00
hmac_test_sha256_vectors 10.600s 263.788us 1 1 100.00
hmac_test_sha384_vectors 398.390s 16789.628us 1 1 100.00
hmac_test_sha512_vectors 30.720s 897.923us 1 1 100.00
hmac_test_hmac256_vectors 9.490s 298.132us 1 1 100.00
hmac_test_hmac384_vectors 10.890s 1197.956us 1 1 100.00
hmac_test_hmac512_vectors 16.180s 464.513us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 17.270s 601.286us 1 1 100.00
hmac_long_msg 30.920s 3264.889us 1 1 100.00
hmac_back_pressure 70.300s 7998.845us 1 1 100.00
hmac_datapath_stress 885.100s 9067.862us 1 1 100.00
hmac_burst_wr 23.530s 10712.587us 1 1 100.00
hmac_error 128.380s 12753.133us 1 1 100.00
hmac_wipe_secret 50.870s 3043.588us 1 1 100.00
hmac_test_sha256_vectors 10.600s 263.788us 1 1 100.00
hmac_test_sha384_vectors 398.390s 16789.628us 1 1 100.00
hmac_test_sha512_vectors 30.720s 897.923us 1 1 100.00
hmac_test_hmac256_vectors 9.490s 298.132us 1 1 100.00
hmac_test_hmac384_vectors 10.890s 1197.956us 1 1 100.00
hmac_test_hmac512_vectors 16.180s 464.513us 1 1 100.00
hmac_stress_all 1426.750s 170372.507us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1426.750s 170372.507us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.830s 26.272us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.830s 38.055us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.050s 714.392us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.050s 714.392us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.990s 22.348us 1 1 100.00
hmac_csr_rw 1.070s 113.049us 1 1 100.00
hmac_csr_aliasing 1.960s 144.248us 1 1 100.00
hmac_same_csr_outstanding 2.300s 506.590us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.990s 22.348us 1 1 100.00
hmac_csr_rw 1.070s 113.049us 1 1 100.00
hmac_csr_aliasing 1.960s 144.248us 1 1 100.00
hmac_same_csr_outstanding 2.300s 506.590us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.310s 260.786us 1 1 100.00
hmac_tl_intg_err 2.780s 199.598us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.780s 199.598us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 17.270s 601.286us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.190s 29.796us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 241.180s 104282.984us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.240s 81.871us 1 1 100.00